Fix reading CSRs.

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 8f7b85f747946eb0fc698257c8d722190d0ace61..03588f3e557d00927db40d092d08b8c44ebc1922 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -66,10 +66,6 @@ void processor_t::step(size_t n)
     n = std::min(n, (size_t) 11);
   }
 
-  if (debug) {
-    fprintf(stderr, "step(%ld)\n", n);
-  }
-
   while (n > 0) {
     size_t instret = 0;
     reg_t pc = state.pc;

diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index b181e27a31fd47860e10a8d7da707cc099cbf58c..d8800f8aec1f4732e360d6314f83942d65d81d59 100644 (file)
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -481,6 +481,7 @@ class register_read_op_t : public operation_t
             return true;
           }
           gs.set_interrupt(0);
+          return false;
 
         case 1:
           gs.start_packet();

diff --git a/tests/gdbserver.py b/tests/gdbserver.py
index c3c2ecad016241087e6e6bb3bb51e0cacefbcaca..ac191d5cd2bfdf6c841e2ad225f6e322df64ac72 100755 (executable)
--- a/tests/gdbserver.py
+++ b/tests/gdbserver.py
@@ -58,12 +58,12 @@ class DebugTest(unittest.TestCase):
         # mcpuid (which is going to be renamed to misa in any case).
         #self.assertRegexpMatches(output, ".*mcpuid *0x80")
 
-        # The time register should always be changing.
-        last_time = None
+        # The instret register should always be changing.
+        last_instret = None
         for _ in range(5):
-            time = self.gdb.p("$time")
-            self.assertNotEqual(time, last_time)
-            last_time = time
+            instret = self.gdb.p("$instret")
+            self.assertNotEqual(instret, last_instret)
+            last_instret = instret
             self.gdb.command("stepi")
 
 class RegsTest(unittest.TestCase):