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Fixed masking/casting logic in commit log printf.
author
Christopher Celio
<celio@eecs.berkeley.edu>
Tue, 27 Jan 2015 08:32:57 +0000
(
00:32
-0800)
committer
Christopher Celio
<celio@eecs.berkeley.edu>
Tue, 27 Jan 2015 08:32:57 +0000
(
00:32
-0800)
riscv/processor.cc
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diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index 78cb3f535d018b18fbe64260fbddc7f6069a8bd7..0a344465df6b39ddf981e22b8c28f3ea4f67eeb2 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-127,14
+127,16
@@
static void commit_log(state_t* state, reg_t pc, insn_t insn)
{
#ifdef RISCV_ENABLE_COMMITLOG
if (state->sr & SR_EI) {
{
#ifdef RISCV_ENABLE_COMMITLOG
if (state->sr & SR_EI) {
+ uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
if (state->log_reg_write.addr) {
if (state->log_reg_write.addr) {
- uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
-
fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIx64 " 0x%016" PRIx64 "\n"
,
-
pc,
insn.bits() & mask,
+ fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
+
pc
,
+ insn.bits() & mask,
state->log_reg_write.addr & 1 ? 'f' : 'x',
state->log_reg_write.addr & 1 ? 'f' : 'x',
- state->log_reg_write.addr >> 1, state->log_reg_write.data);
+ state->log_reg_write.addr >> 1,
+ state->log_reg_write.data);
} else {
} else {
- fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits());
+ fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits()
& mask
);
}
}
state->log_reg_write.addr = 0;
}
}
state->log_reg_write.addr = 0;