[xcc, sim] added rvc insn c.li; misc fixes

diff --git a/riscv/execute.h b/riscv/execute.h
index 2fb595e4860de1e7595b264e27f8286d02fcaaa1..9427ee9b340f2d9dfee9e7f5920479710c494539 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -6,6 +6,11 @@ switch((insn.bits >> 0x0) & 0x7f)
     #include "insns/c_addi.h"
     break;
   }
+  case 0x1:
+  {
+    #include "insns/c_li.h"
+    break;
+  }
   case 0x3:
   {
     switch((insn.bits >> 0x7) & 0x7)
@@ -599,6 +604,11 @@ switch((insn.bits >> 0x0) & 0x7f)
     #include "insns/c_addi.h"
     break;
   }
+  case 0x21:
+  {
+    #include "insns/c_li.h"
+    break;
+  }
   case 0x23:
   {
     switch((insn.bits >> 0x7) & 0x7)
@@ -1019,6 +1029,11 @@ switch((insn.bits >> 0x0) & 0x7f)
     #include "insns/c_addi.h"
     break;
   }
+  case 0x41:
+  {
+    #include "insns/c_li.h"
+    break;
+  }
   case 0x43:
   {
     switch((insn.bits >> 0x7) & 0x7)
@@ -1550,6 +1565,11 @@ switch((insn.bits >> 0x0) & 0x7f)
     #include "insns/c_addi.h"
     break;
   }
+  case 0x61:
+  {
+    #include "insns/c_li.h"
+    break;
+  }
   case 0x63:
   {
     switch((insn.bits >> 0x7) & 0x7)

diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h
new file mode 100644 (file)
index 0000000..892f473
--- /dev/null
+++ b/riscv/insns/c_li.h
@@ -0,0 +1,2 @@
+require_rvc;
+CRD = SIMM;

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 5d516bc59981d7c6584febf0924b93a626e3b949..efaea3e3da839ab8ffe31de3299215a3c697483e 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -25,7 +25,10 @@ public:
     uint16_t hi = *(uint16_t*)(mem+addr+2);
 
     insn_t insn; 
-    insn.bits = ((uint32_t)hi << 16) | lo;
+    insn.bits = lo;
+    if((lo & 0x3) == 0x3)
+      insn.bits |= (uint32_t)hi << 16;
+
     return insn;
   }