Serialize simulator on ERET

This guarantees interrupts will eventually be taken.

diff --git a/riscv/decode.h b/riscv/decode.h
index 1dfeac1bf7c715be628ff17f9c8338ba499cdab6..f8437cae5f178c87c510f5aca039cf2b7c2e7069 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -198,6 +198,12 @@ private:
        npc = sext_xlen(x); \
      } while(0)
 
+#define set_pc_and_serialize(x) \
+  do { set_pc(x); /* check alignment */ \
+       npc = PC_SERIALIZE; \
+       STATE.pc = (x); \
+     } while(0)
+
 #define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */
 
 /* Convenience wrappers to simplify softfloat code sequences */

diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h
index eacf5bee5ff9cad6ce9106a8176b1b2281b99a18..c3561d38e45a8f6cfce93df9ccca339e89b5eb72 100644 (file)
--- a/riscv/insns/sret.h
+++ b/riscv/insns/sret.h
@@ -1,8 +1,8 @@
 require_privilege(PRV_S);
 switch (STATE.prv)
 {
-  case PRV_S: set_pc(p->get_state()->sepc); break;
-  case PRV_M: set_pc(p->get_state()->mepc); break;
+  case PRV_S: set_pc_and_serialize(p->get_state()->sepc); break;
+  case PRV_M: set_pc_and_serialize(p->get_state()->mepc); break;
   default: abort();
 }