Only allow SIP.SSIP to be toggled if the interrupt is delegated

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 75f4002bea9535519952d9bec51f8c314d7772e3..7417acfbcd4b8e82963ca436882496cf62da6d14 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -374,7 +374,7 @@ void processor_t::set_csr(int which, reg_t val)
       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
     }
     case CSR_SIP: {
-      reg_t mask = MIP_SSIP;
+      reg_t mask = MIP_SSIP & state.mideleg;
       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
     }
     case CSR_SIE: