Commit log now prints while interrupts are enabled.
[riscv-isa-sim.git] / README
2013-05-15 Yunsup Leechange riscv-isa-run to spike in documentation
2013-04-24 Yunsup Leefixes to correctly simulate the vector unit
2013-03-26 Andrew Watermanupdate ancient README
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2010-08-19 Andrew Waterman[pk,fesvr] improved proxykernel build system