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Use new NaN discipline
[riscv-isa-sim.git]
/
hwacha
/
hwacha.cc
2015-03-16
Yunsup Lee
bugfix in raising accelerator interrupts
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2014-12-05
Andrew Waterman
zero-extend 32b instructions for vxcptaux
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2014-11-25
Andrew Waterman
Factor out the dummy RoCC accelerator
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2013-11-30
Quan Nguyen
Add vsetprec instruction prototype
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2013-11-25
Quan Nguyen
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-11-06
Yunsup Lee
correctly trap when SR_EA is disabled
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2013-11-05
Albert Ou
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-10-29
Yunsup Lee
include stdexcept
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2013-10-19
Yunsup Lee
more hwacha supervisor stuff
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2013-10-19
Yunsup Lee
refactor disassembler, and add hwacha disassembler
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2013-10-18
Yunsup Lee
catch trap_illegal_instruction in hwacha
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2013-10-18
Yunsup Lee
add hwacha exception support
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2013-10-16
Yunsup Lee
use reset virtual method
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2013-10-16
Yunsup Lee
use uint32_t for vl
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2013-10-16
Yunsup Lee
revamp hwacha; now runs in physical mode
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projects / riscv-isa-sim.git / history