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Use new NaN discipline
[riscv-isa-sim.git]
/
hwacha
/
insns
/
vf.h
2014-12-05
Andrew Waterman
Support 2/4/6/8-byte instructions
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2014-02-04
Quan Nguyen
Move half precision instructions, add vfmsv, vfmvv
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2013-11-25
Quan Nguyen
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-11-05
Albert Ou
Fix declaration of half-precision instructions
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2013-11-05
Albert Ou
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-10-19
Yunsup Lee
refactor disassembler, and add hwacha disassembler
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2013-10-18
Yunsup Lee
add hwacha exception support
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2013-10-16
Yunsup Lee
revamp hwacha; now runs in physical mode
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2013-07-26
Andrew Waterman
Rip out Hwacha for now
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projects / riscv-isa-sim.git / history