projects / riscv-isa-sim.git / history
| 2014-04-03 | Stephen Twigg | Merge branch 'tm' | blob | commitdiff | raw |
| 2014-04-03 | Stephen Twigg | Sync encoding in opcodes | blob | commitdiff | raw |
| 2014-02-04 | Quan Nguyen | Move half precision instructions, add vfmsv, vfmvv | blob | commitdiff | raw | diff to current |
| 2013-11-25 | Quan Nguyen | Merge branch 'master' of github.com:ucb-bar/riscv-isa... | blob | commitdiff | raw | diff to current |
| 2013-11-21 | Yunsup Lee | fix slli/slliw encoding bug | blob | commitdiff | raw | diff to current |
| 2013-11-05 | Albert Ou | Merge branch 'master' of github.com:ucb-bar/riscv-isa... | blob | commitdiff | raw | diff to current |
| 2013-10-18 | Yunsup Lee | can't execute frsr/fssr on ut | blob | commitdiff | raw | diff to current |
| 2013-10-16 | Yunsup Lee | revamp hwacha; now runs in physical mode | blob | commitdiff | raw | diff to current |