Disasm now translates xor x0,x0,x0 as a machine-generated bubble ("-").
[riscv-isa-sim.git] / hwacha /
2014-01-21 Quan NguyenMerge branch 'confprec'
2013-12-17 Andrew WatermanSpeed things up quite a bit
2013-11-30 Quan NguyenRemove debug printf in vsetprec
2013-11-30 Quan NguyenAdd vsetprec instruction prototype
2013-11-25 Andrew WatermanUpdate to new privileged ISA
2013-11-25 Quan NguyenMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-11-21 Yunsup Leefix slli/slliw encoding bug
2013-11-06 Yunsup Leecorrectly trap when SR_EA is disabled
2013-11-05 Albert OuFix declaration of half-precision instructions
2013-11-05 Albert OuRe-add Hwacha header file
2013-11-05 Albert OuImplement "half-baked" half-precision instruction subse...
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-10-29 Yunsup Leeinclude stdexcept
2013-10-22 Yunsup Leeclarify vxcptsave/vxctkill semantics
2013-10-19 Yunsup Leeimplement vxcptsave/vxcptrestore
2013-10-19 Yunsup Leemore hwacha supervisor stuff
2013-10-19 Yunsup Leerefactor disassembler, and add hwacha disassembler
2013-10-18 Yunsup Leecan't execute frsr/fssr on ut
2013-10-18 Yunsup Leeor into control thread's fp exceptions
2013-10-18 Yunsup Leecatch trap_illegal_instruction in hwacha
2013-10-18 Yunsup Leeadd hwacha exception support
2013-10-16 Yunsup Leefix maxvl calc logic
2013-10-16 Yunsup Leeuse reset virtual method
2013-10-16 Yunsup Leeuse uint32_t for vl
2013-10-16 Yunsup Leerevamp hwacha; now runs in physical mode
2013-07-27 Andrew WatermanRemove more vector stuff
2013-07-26 Andrew WatermanRip out Hwacha for now