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reorganise twin-predication
[riscv-isa-sim.git]
/
id_regs.py
2018-10-04
Luke Kenneth Casso...
reorganise twin-predication
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2018-10-04
Luke Kenneth Casso...
big reorganisation to support twin-predication
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2018-10-03
Luke Kenneth Casso...
add in twin-predication identification
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2018-10-02
Luke Kenneth Casso...
start work on parallelsing LOAD, pass in parameter...
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2018-10-01
Luke Kenneth Casso...
skip parallelisation of complex LR/SC operations
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2018-10-01
Luke Kenneth Casso...
identify type of instruction with additional #defines
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2018-09-30
Luke Kenneth Casso...
add a #define to id_regs.py which indicates name of...
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2018-09-30
Luke Kenneth Casso...
list of instructions to avoid parallelising
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2018-09-30
Luke Kenneth Casso...
add compressed-identifying patterns to id_regs.py
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2018-09-30
Luke Kenneth Casso...
yuk. break id_regs.py being a generic tool by skipping...
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2018-09-29
Luke Kenneth Casso...
also arrange for id_regs.py to identify compressed...
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2018-09-26
Luke Kenneth Casso...
ok this is tricky: an extra parameter has to be passed...
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2018-09-26
Luke Kenneth Casso...
easier to #define USING_NOREGS if the opcode does not...
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2018-09-26
Luke Kenneth Casso...
include auto-generated identification of use of registe...
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2018-09-25
Luke Kenneth Casso...
skip id_reg.py parsing its own output; stop outputting...
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2018-09-25
Luke Kenneth Casso...
change to instruction template parsing, create one...
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2018-09-24
Luke Kenneth Casso...
create #defines from identified registers, per opcode
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2018-09-24
Luke Kenneth Casso...
clarify docstring on id_regs.py
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2018-09-24
Luke Kenneth Casso...
add function identifying the registers in each emulated...
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2018-09-24
Luke Kenneth Casso...
identify instructions, plan: extract registers
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