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New RV64C proposal
[riscv-isa-sim.git]
/
riscv
/
encoding.h
2015-06-01
Andrew Waterman
New RV64C proposal
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2015-05-15
Andrew Waterman
Merge pull request #20 from palmer-dabbelt/package
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2015-05-14
Andrew Waterman
Fix VM, MIP encoding
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2015-05-09
Andrew Waterman
Upgrade to privileged architecture 1.7
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2015-04-04
Andrew Waterman
Support setting ISA/subsets with --isa flag
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2015-03-31
Andrew Waterman
Implement RVC draft
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2015-03-27
Andrew Waterman
New virtual memory implementation (Sv39)
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2015-03-17
Andrew Waterman
Merge [shm]call into ecall, [shm]ret into eret
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2015-03-13
Andrew Waterman
Use hcall instead of mcall
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2015-03-13
Andrew Waterman
Implement PTE referenced/dirty bits
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2014-11-22
Yunsup Lee
Revert "Enable support for the four custom instructions"
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2014-10-24
Yunsup Lee
Merge pull request #4 from arunthomas/custom_inst
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2014-10-23
Arun Thomas
Enable support for the four custom instructions
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2014-04-03
Stephen Twigg
Merge branch 'tm'
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2014-04-03
Stephen Twigg
Sync encoding in opcodes
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2014-03-18
Andrew Waterman
Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
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2014-03-12
Andrew Waterman
New FP encoding
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2014-03-07
Andrew Waterman
Add fclass.{s|d} instructions
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2014-02-15
Andrew Waterman
Renumber uarch CSRs into custom CSR space
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2014-02-06
Yunsup Lee
commit missing definitions for uarch counters
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2014-01-22
Andrew Waterman
Use auto-generated trap cause numbers
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2014-01-14
Andrew Waterman
Improve performance for branchy code
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2013-12-09
Andrew Waterman
New RDCYCLE encoding
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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