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[riscv-isa-sim.git] / riscv / insn_template_sv.cc

2018-10-04	Luke Kenneth Casso...	reorganise twin-predication	blob \| commitdiff \| raw
2018-10-04	Luke Kenneth Casso...	big reorganisation to support twin-predication	blob \| commitdiff \| raw \| diff to current
2018-10-03	Luke Kenneth Casso...	add in twin-predication identification	blob \| commitdiff \| raw \| diff to current
2018-10-03	Luke Kenneth Casso...	decided not to change the behaviour of LOAD/STORE	blob \| commitdiff \| raw \| diff to current
2018-10-02	Luke Kenneth Casso...	start work on parallelsing LOAD, pass in parameter...	blob \| commitdiff \| raw \| diff to current
2018-10-02	Luke Kenneth Casso...	debug print for floating-point regs	blob \| commitdiff \| raw \| diff to current
2018-10-01	Luke Kenneth Casso...	add comment explaining why invert isnt done in zeroing...	blob \| commitdiff \| raw \| diff to current
2018-10-01	Luke Kenneth Casso...	add comment explaining use of insn._rd() in zeroing	blob \| commitdiff \| raw \| diff to current
2018-10-01	Luke Kenneth Casso...	whoops vloop continuation logic the wrong way round	blob \| commitdiff \| raw \| diff to current
2018-09-30	Luke Kenneth Casso...	update template comment	blob \| commitdiff \| raw \| diff to current
2018-09-30	Luke Kenneth Casso...	lots of debugging of predication, found other errors	blob \| commitdiff \| raw \| diff to current
2018-09-30	Luke Kenneth Casso...	add sv support for zeroing predication in dest register	blob \| commitdiff \| raw \| diff to current
2018-09-30	Luke Kenneth Casso...	add in predication to sv instruction execution	blob \| commitdiff \| raw \| diff to current
2018-09-30	Luke Kenneth Casso...	start linking in predication into sv	blob \| commitdiff \| raw \| diff to current
2018-09-30	Luke Kenneth Casso...	use an alternative logic for detecting scalar / loop-end	blob \| commitdiff \| raw \| diff to current
2018-09-29	Luke Kenneth Casso...	fix bug in sv template where FRS2 was checking rs3	blob \| commitdiff \| raw \| diff to current
2018-09-29	Luke Kenneth Casso...	add checks for RVC registers to sv template	blob \| commitdiff \| raw \| diff to current
2018-09-29	Luke Kenneth Casso...	a LOT of debugging and fixing, sv loop actually working	blob \| commitdiff \| raw \| diff to current
2018-09-29	Luke Kenneth Casso...	reorganise from moving sv_pred_* and sv_reg_* tables...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	save some cpu cycles by \|ing the checks for vectorop...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	whoops vectorop has to be \|= not &= to accumulate ...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	cache the sv redirected register values on each loop	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	remembered that the use of sv registers have to be...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	ok this is tricky: an extra parameter has to be passed...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	check if register redirection is active, and if vectori...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	comment why sv_insn_t is set up the way it is; add...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	shuffle things around a bit for sv, put rv32/64_name...	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike

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