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[xcc] minor performance tweaks
[riscv-isa-sim.git] / riscv / insns / jalr_c.h
2011-06-11 Andrew Waterman[xcc] instructions now set PC explicitly blob | commitdiff | raw
2011-04-15 Andrew Waterman[sim] fixed jalr immediate bug blob | commitdiff | raw | diff to current
2011-01-12 Andrew Waterman[sim] fix jalr bug blob | commitdiff | raw | diff to current
2010-11-22 Andrew Waterman[xcc, sim, pk, opcodes] new instruction encoding! blob | commitdiff | raw | diff to current
2010-09-21 Andrew Waterman[xcc, sim] changed instruction format so imm12 subs... blob | commitdiff | raw | diff to current
2010-07-29 Andrew Waterman[sim,xcc] Changed instruction format to RISC-V blob | commitdiff | raw | diff to current
Simple-V augmented version of spike