git.libre-soc.org Git - riscv-isa-sim.git/history

2017-02-15	Tim Newsome	Implement resume (untested).	blob \| commitdiff \| raw
2017-02-11	Tim Newsome	Entering debug mode now jumps to "dynamic rom"	blob \| commitdiff \| raw \| diff to current
2014-01-21	Quan Nguyen	Merge branch 'confprec'	blob \| commitdiff \| raw
2013-11-25	Andrew Waterman	Update to new privileged ISA	blob \| commitdiff \| raw
2013-11-25	Quan Nguyen	Merge branch 'master' of github.com:ucb-bar/riscv-isa...	blob \| commitdiff \| raw \| diff to current
2013-11-21	Yunsup Lee	fix slli/slliw encoding bug	blob \| commitdiff \| raw \| diff to current
2013-10-28	Quan Nguyen	Add missing fcvt opcodes through riscv-opcodes	blob \| commitdiff \| raw \| diff to current
2013-10-18	Quan Nguyen	Add empty opcode header files for half-precision	blob \| commitdiff \| raw \| diff to current
2013-09-21	Andrew Waterman	Update ISA encoding and AUIPC semantics	blob \| commitdiff \| raw \| diff to current
2013-09-15	Andrew Waterman	ISA changes	blob \| commitdiff \| raw \| diff to current
2013-09-11	Andrew Waterman	Add AMOXOR	blob \| commitdiff \| raw \| diff to current
2013-09-11	Andrew Waterman	Implement zany immediates	blob \| commitdiff \| raw \| diff to current
2013-09-10	Andrew Waterman	Add rd field to JAL; drop J	blob \| commitdiff \| raw \| diff to current
2013-08-08	Andrew Waterman	Rename MTFSR/MFFSR to FSSR/FRSR	blob \| commitdiff \| raw \| diff to current
2013-08-08	Andrew Waterman	Swap J and JALR encoding	blob \| commitdiff \| raw \| diff to current
2013-07-27	Andrew Waterman	New supervisor mode	blob \| commitdiff \| raw \| diff to current
2013-07-27	Andrew Waterman	Rename MFTX/MXTF to FMV	blob \| commitdiff \| raw \| diff to current
2013-07-26	Andrew Waterman	Rip out Hwacha for now	blob \| commitdiff \| raw \| diff to current
2013-07-26	Andrew Waterman	Rip out RVC for now	blob \| commitdiff \| raw \| diff to current
2013-07-25	Andrew Waterman	Remove JALR static hints	blob \| commitdiff \| raw \| diff to current
2013-04-17	Andrew Waterman	add AUIPC insn; remove RDNPC insn	blob \| commitdiff \| raw \| diff to current
2013-03-30	Andrew Waterman	add load-reserved/store-conditional instructions	blob \| commitdiff \| raw \| diff to current
2013-03-27	Andrew Waterman	opcodes.h must only contain DECLARE_INSN() lines	blob \| commitdiff \| raw \| diff to current
2013-03-26	Andrew Waterman	add BSD license	blob \| commitdiff \| raw \| diff to current
2012-03-24	Andrew Waterman	new supervisor mode	blob \| commitdiff \| raw \| diff to current
2012-03-19	Andrew Waterman	update vector fences	blob \| commitdiff \| raw \| diff to current
2012-03-18	Yunsup Lee	clean up vector exception instructions	blob \| commitdiff \| raw \| diff to current
2012-03-14	Yunsup Lee	add more instructions for vector exception handling	blob \| commitdiff \| raw \| diff to current
2012-03-14	Yunsup Lee	add vvcfg,vtcfg	blob \| commitdiff \| raw \| diff to current
2012-03-13	Yunsup Lee	opcodes cleanup	blob \| commitdiff \| raw \| diff to current
2012-03-10	Yunsup Lee	slight change to vector supervisor instructions	blob \| commitdiff \| raw \| diff to current
2012-03-03	Yunsup Lee	new instructions to handle vector exceptions	blob \| commitdiff \| raw \| diff to current
2011-11-11	Andrew Waterman	Changed MFTX to use rs1 for its source	blob \| commitdiff \| raw \| diff to current
2011-06-20	Andrew Waterman	temporary undoing of renaming	blob \| commitdiff \| raw \| diff to current
2011-06-13	Andrew Waterman	[sim] renamed to riscv-isa-run	blob \| commitdiff \| raw
2011-06-11	Andrew Waterman	[sim, opcodes] made sim more decoupled from opcodes	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike

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