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Merge pull request #117 from riscv/multicore_debug
[riscv-isa-sim.git]
/
riscv
/
rocc.cc
2015-09-08
Andrew Waterman
Refer to LICENSE in some newer source files
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2013-11-25
Quan Nguyen
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-11-06
Yunsup Lee
correctly trap when SR_EA is disabled
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2013-11-05
Albert Ou
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-10-19
Yunsup Lee
refactor disassembler, and add hwacha disassembler
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2013-10-18
Yunsup Lee
fix custom-1 rocc encoding
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2013-10-16
Yunsup Lee
revamp hwacha; now runs in physical mode
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2013-10-15
Stephen Twigg
Fix bug where xs2 was not being properly respected.
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2013-09-27
Andrew Waterman
Use WRITE_RD/WRITE_FRD macros to write registers
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2013-08-13
Andrew Waterman
Implement RoCC and add a dummy RoCC
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