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reorganise twin-predication
[riscv-isa-sim.git]
/
riscv
/
sv.cc
2018-10-04
Luke Kenneth Casso...
reorganise twin-predication
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2018-10-04
Luke Kenneth Casso...
big reorganisation to support twin-predication
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2018-10-03
Luke Kenneth Casso...
decided not to change the behaviour of LOAD/STORE
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2018-10-02
Luke Kenneth Casso...
start work on parallelsing LOAD, pass in parameter...
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2018-10-01
Luke Kenneth Casso...
whoops vloop continuation logic the wrong way round
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2018-09-30
Luke Kenneth Casso...
lots of debugging of predication, found other errors
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2018-09-30
Luke Kenneth Casso...
add sv support for zeroing predication in dest register
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2018-09-30
Luke Kenneth Casso...
add in predication to sv instruction execution
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2018-09-30
Luke Kenneth Casso...
use an alternative logic for detecting scalar / loop-end
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2018-09-29
Luke Kenneth Casso...
a LOT of debugging and fixing, sv loop actually working
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2018-09-29
Luke Kenneth Casso...
reorganise from moving sv_pred_* and sv_reg_* tables...
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2018-09-29
Luke Kenneth Casso...
have to move SV CSRs into processor_t
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2018-09-27
Luke Kenneth Casso...
add sv predication function
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2018-09-26
Luke Kenneth Casso...
remembered that the use of sv registers have to be...
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2018-09-26
Luke Kenneth Casso...
clarify comments on (key strategic) sv_insn_t::remap...
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2018-09-26
Luke Kenneth Casso...
actually implement sv register re-mapping
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2018-09-26
Luke Kenneth Casso...
ok this is tricky: an extra parameter has to be passed...
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2018-09-26
Luke Kenneth Casso...
move sv remap function to sv.cc (not inline)
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2018-09-26
Luke Kenneth Casso...
check if register redirection is active, and if vectori...
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2018-09-25
Luke Kenneth Casso...
rename sv vlen to sv voffs, add csr and reg tables
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