add BSD license
[riscv-isa-sim.git] / riscv / trap.h
2013-03-26 Andrew Watermanadd BSD license
2012-03-24 Andrew Watermannew supervisor mode
2011-11-11 Andrew WatermanChanged supervisor mode
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-18 Yunsup Lee[opcodes,pk,sim] add more vector traps (for #banks...
2011-04-12 Andrew Waterman[sim,pk] fixed minor pk bugs and trap codes
2011-04-10 Yunsup Lee[sim] add vector traps to vector instructions
2011-04-10 Andrew Waterman[sim,pk] reorganized status register
2011-03-25 Andrew Waterman[xcc,pk,opcodes,sim] updated encoding/insn names
2011-02-05 Andrew Waterman[sim,pk] added interrupt-pending field to cause reg
2010-09-11 Andrew Waterman[sim, pk] cleaned up exception vectors and FP exc flags
2010-08-05 Andrew Waterman[xcc,pk,sim] Added first part of FP support
2010-07-19 Andrew WatermanReorganized directory structure