Commit log now prints while interrupts are enabled.
[riscv-isa-sim.git] / spike /
2014-04-24 Andrew Watermanfix disassembly of bnez and friends
2014-03-07 Andrew WatermanAdd fclass.{s|d} instructions
2014-02-06 Andrew WatermanFix disassembly of JAL
2014-02-01 Andrew WatermanFix linking on Darwin
2014-01-29 Christopher CelioDisasm now translates xor x0,x0,x0 as a machine-generat...
2014-01-28 Andrew WatermanForce extension loaders to be linked in
2014-01-27 Andrew WatermanEnable runtime loading of dynamic library with --extlib
2014-01-27 Andrew WatermanEliminate hwacha <-> riscv circular dependence