projects / riscv-isa-sim.git / history
| 2015-10-20 | Andrew Waterman | Update to hopefully final RVC 1.9 encoding | blob | commitdiff | raw |
| 2015-10-06 | Andrew Waterman | more work towards RVC 1.8 | blob | commitdiff | raw | diff to current |
| 2015-10-02 | Andrew Waterman | work towards rvc 1.8 | blob | commitdiff | raw | diff to current |
| 2015-09-04 | Andrew Waterman | Move towards RVC v1.8 | blob | commitdiff | raw | diff to current |
| 2015-06-01 | Andrew Waterman | New RV64C proposal | blob | commitdiff | raw | diff to current |
| 2015-03-31 | Andrew Waterman | Implement RVC draft | blob | commitdiff | raw | diff to current |
| 2015-01-05 | Andrew Waterman | canonicalize assembler pseudo-ops | blob | commitdiff | raw | diff to current |
| 2015-01-05 | Andrew Waterman | Disassemble jalr x0, x1, 0 as ret | blob | commitdiff | raw | diff to current |
| 2014-12-20 | Andrew Waterman | Support building from within root directory | blob | commitdiff | raw | diff to current |