Merge pull request #156 from p12nGH/noncontiguous_harts
[riscv-isa-sim.git] / spike_main / disasm.cc
2017-11-16 Andrew WatermanMerge pull request #156 from p12nGH/noncontiguous_harts
2017-11-06 Kito ChengImplement Q extension for disassembler (#153)
2017-11-04 Andrew WatermanFix disassembly of c.li 0
2017-08-10 Palmer DabbeltCorrect c.li and c.lui disassembly (#118)
2017-05-17 Palmer DabbeltMerge remote-tracking branch 'origin/priv-1.10'
2017-05-16 Palmer DabbeltMerge remote-tracking branch 'origin/debug-0.13' into...
2017-04-25 Andrew WatermanFMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
2017-04-25 Andrew WatermanRemove hret instruction
2016-06-29 Andrew WatermanDisassemble RVC instructions based on XLEN
2016-06-03 neuschaeferMinor usability improvements (#48)
2016-04-28 Andrew WatermanRemove MTIME[CMP]; add RTC device
2016-04-20 Andrew WatermanSplit ERET into URET, SRET, HRET, MRET
2015-10-20 Andrew WatermanUpdate to hopefully final RVC 1.9 encoding
2015-10-06 Andrew Watermanmore work towards RVC 1.8
2015-10-02 Andrew Watermanwork towards rvc 1.8
2015-09-04 Andrew WatermanMove towards RVC v1.8
2015-06-01 Andrew WatermanNew RV64C proposal
2015-03-31 Andrew WatermanImplement RVC draft
2015-01-05 Andrew Watermancanonicalize assembler pseudo-ops
2015-01-05 Andrew WatermanDisassemble jalr x0, x1, 0 as ret
2014-12-20 Andrew WatermanSupport building from within root directory