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Rename riscv-dis to spike-dasm
2015-01-05
Andrew Waterman
Rename riscv-dis to spike-dasm
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2015-01-05
Andrew Waterman
Disassemble jalr x0, x1, 0 as ret
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2015-01-03
Andrew Waterman
Require 4-byte instruction alignment until RVC is reimplemented
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2015-01-03
Andrew Waterman
On misaligned fetch, set EPC to target, not branch...
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2015-01-02
Andrew Waterman
Reduce dependences on auto-generated code
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projects / riscv-isa-sim.git / search