git.libre-soc.org Git - riscv-isa-sim.git/search

2017-06-07	Andrew Waterman	Forbid S-mode execution from user memory	commit \| commitdiff \| tree
2017-05-03	Kito Cheng	Add missing include for devices.h	commit \| commitdiff \| tree
2016-12-30	Brian Campbell	Only read exception flag in gdb register read/write...	commit \| commitdiff \| tree
2016-12-21	Brian Campbell	Fix gdb communication error (#82)	commit \| commitdiff \| tree
2016-12-17	Stefan O'Rear	Use correct format codes for reg_t and size_t	commit \| commitdiff \| tree
2016-12-16	Tim Newsome	Fix single stepping over faulting instructions. (#80)	commit \| commitdiff \| tree
2016-12-12	Tim Newsome	Reuse the ebreak constants in encoding.h.	commit \| commitdiff \| tree
2016-12-01	Andy Wright	Added comments about the modified Duff's Device in...	commit \| commitdiff \| tree
2016-11-12	Ben Gamari	Ensure that g++ knows it is building a PCH (#75)	commit \| commitdiff \| tree
2015-01-05	Andrew Waterman	canonicalize assembler pseudo-ops	commit \| commitdiff \| tree
2015-01-05	Andrew Waterman	Rename riscv-dis to spike-dasm	commit \| commitdiff \| tree
2015-01-05	Andrew Waterman	Disassemble jalr x0, x1, 0 as ret	commit \| commitdiff \| tree
2015-01-03	Andrew Waterman	Require 4-byte instruction alignment until RVC is reimplemented	commit \| commitdiff \| tree
2015-01-03	Andrew Waterman	On misaligned fetch, set EPC to target, not branch...	commit \| commitdiff \| tree
2015-01-02	Andrew Waterman	Reduce dependences on auto-generated code	commit \| commitdiff \| tree

Simple-V augmented version of spike