| 2018-10-10 |
Luke Kenneth Casson... | add operators library to contain operator-overloads...
|
commit | commitdiff | tree |
| 2018-10-09 |
Luke Kenneth Casson... | get predicated-vectorised branch working
|
commit | commitdiff | tree |
| 2018-10-09 |
Luke Kenneth Casson... | save branch address and predication merged result,...
|
commit | commitdiff | tree |
| 2018-10-09 |
Luke Kenneth Casson... | add explanatory comment
|
commit | commitdiff | tree |
| 2018-10-09 |
Luke Kenneth Casson... | add explanatory comment
|
commit | commitdiff | tree |
| 2018-10-09 |
Luke Kenneth Casson... | start adding explicit twin-predicated branch identification...
|
commit | commitdiff | tree |
| 2018-10-09 |
Luke Kenneth Casson... | extend sv register file from 64 to 128 after discussion.
|
commit | commitdiff | tree |
| 2018-10-07 |
Luke Kenneth Casson... | override setpc macro so that sv can redirect it in...
|
commit | commitdiff | tree |
| 2018-10-07 |
Luke Kenneth Casson... | swap #ifdef USING_NOREGS so that it is possible to...
|
commit | commitdiff | tree |
| 2018-10-07 |
Luke Kenneth Casson... | add rd bit-setting function
|
commit | commitdiff | tree |
| 2018-10-07 |
Luke Kenneth Casson... | add extra debug printing for c.lwsp
|
commit | commitdiff | tree |
| 2018-10-07 |
Luke Kenneth Casson... | add rvc_swsp_imm sv overload, provides vector unit...
|
commit | commitdiff | tree |
| 2018-10-06 |
Luke Kenneth Casson... | c.swsp and c.fswsp predication and offset enabling
|
commit | commitdiff | tree |
| 2018-10-06 |
Luke Kenneth Casson... | allow x2 (sp) to be redirected in C.LWSP
|
commit | commitdiff | tree |
| 2018-10-06 |
Luke Kenneth Casson... | temporary hack disabling SV in anything other than...
|
commit | commitdiff | tree |
| 2018-10-06 |
Luke Kenneth Casson... | whoops inverted ldsp and lwsp immediates
|
commit | commitdiff | tree |
| 2018-10-06 |
Luke Kenneth Casson... | create ldsp immediate offset overrides
|
commit | commitdiff | tree |
| 2018-10-06 |
Luke Kenneth Casson... | add in predication for immediate, for C.LWSP
|
commit | commitdiff | tree |
| 2018-10-05 |
Luke Kenneth Casson... | reorganise src and dest vector-element offsets
|
commit | commitdiff | tree |
| 2018-10-05 |
Luke Kenneth Casson... | add srcoffs and destoffs sv state, alter CSRs
|
commit | commitdiff | tree |
| 2018-10-04 |
Luke Kenneth Casson... | reorganise twin-predication
|
commit | commitdiff | tree |
| 2018-10-04 |
Luke Kenneth Casson... | big reorganisation to support twin-predication
|
commit | commitdiff | tree |
| 2018-10-03 |
Luke Kenneth Casson... | add in twin-predication identification
|
commit | commitdiff | tree |
| 2018-10-03 |
Luke Kenneth Casson... | decided not to change the behaviour of LOAD/STORE
|
commit | commitdiff | tree |
| 2018-10-02 |
Luke Kenneth Casson... | start work on parallelsing LOAD, pass in parameter...
|
commit | commitdiff | tree |
| 2018-10-02 |
Luke Kenneth Casson... | debug print for floating-point regs
|
commit | commitdiff | tree |
| 2018-10-01 |
Luke Kenneth Casson... | add comment explaining why invert isnt done in zeroing...
|
commit | commitdiff | tree |
| 2018-10-01 |
Luke Kenneth Casson... | add comment explaining use of insn._rd() in zeroing
|
commit | commitdiff | tree |
| 2018-10-01 |
Luke Kenneth Casson... | whoops vloop continuation logic the wrong way round
|
commit | commitdiff | tree |
| 2018-10-01 |
Luke Kenneth Casson... | skip parallelisation of complex LR/SC operations
|
commit | commitdiff | tree |
| 2018-10-01 |
Luke Kenneth Casson... | identify type of instruction with additional #defines
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | add a #define to id_regs.py which indicates name of...
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | list of instructions to avoid parallelising
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | update template comment
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | lots of debugging of predication, found other errors
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | add sv support for zeroing predication in dest register
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | add in predication to sv instruction execution
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | start linking in predication into sv
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | use an alternative logic for detecting scalar / loop-end
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | add compressed-identifying patterns to id_regs.py
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | fix code template for when SPIKE_SIMPLEV is not defined
|
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth Casson... | yuk. break id_regs.py being a generic tool by skipping...
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | fix bug in sv template where FRS2 was checking rs3
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | add checks for RVC registers to sv template
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | add sv_insn_t overloads for rvc registers
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | also arrange for id_regs.py to identify compressed...
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | a LOT of debugging and fixing, sv loop actually working
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | move SV CSRs to user-read-write
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | add near-duplicate of SV CFG REG CSRs, for predication
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | add implementation of CSR SV CFG regs 0-7
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | assign SV REG CSRs (using new union ability)
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | make sv csr tables a union so they can be assigned...
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | add support for CSR_SVVL to CSRRWI as well
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | fix bug in CSR set SVVL: val has already been looked up
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | add stub for SV REG configs
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | stop a compiler warning
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | reorganise from moving sv_pred_* and sv_reg_* tables...
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | have to move SV CSRs into processor_t
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | add 8 CSRs for registers and predication each
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | whoops dont need separate SVSETVL/SVGETVL CSRs
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | revert addition of svsetvl as an actual opcode, add...
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | Revert "sv setvl as a csr not going to work, add getvl...
|
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth Casson... | Revert "manually add svsetvl instruction"
|
commit | commitdiff | tree |
| 2018-09-28 |
Luke Kenneth Casson... | manually add svsetvl instruction
|
commit | commitdiff | tree |
| 2018-09-28 |
Luke Kenneth Casson... | sv setvl as a csr not going to work, add getvl only
|
commit | commitdiff | tree |
| 2018-09-27 |
Luke Kenneth Casson... | adding sv vector length CSR to processor state, and...
|
commit | commitdiff | tree |
| 2018-09-27 |
Luke Kenneth Casson... | add sv predication function
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | save some cpu cycles by |ing the checks for vectorop...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | whoops vectorop has to be |= not &= to accumulate ...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | cache the sv redirected register values on each loop
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | remembered that the use of sv registers have to be...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | clarify comments on (key strategic) sv_insn_t::remap...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | actually implement sv register re-mapping
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | ok this is tricky: an extra parameter has to be passed...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | move sv remap function to sv.cc (not inline)
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | check if register redirection is active, and if vectorisatio...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | comment why sv_insn_t is set up the way it is; add...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | easier to #define USING_NOREGS if the opcode does not...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | include auto-generated identification of use of registers...
|
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth Casson... | shuffle things around a bit for sv, put rv32/64_name...
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | skip id_reg.py parsing its own output; stop outputting...
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | change to instruction template parsing, create one...
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | add decode.h header to sv.h
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | rename sv vlen to sv voffs, add csr and reg tables
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | add reference to vector length in sv
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | use sv_insn_t class in instruction template
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | add sv_insn_t class (inherits from insn_t)
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | argh cant virtualise rd/rs1-3, due to union usage with...
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | sv: rd, rs1/2/3 become virtual so that sv_insn_t can...
|
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth Casson... | clarify sv cam table
|
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth Casson... | define CSR and register tables for SV
|
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth Casson... | remove unneeded use of AM_CONDITIONAL
|
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth Casson... | add #define for SPIKE_SIMPLEV, re-run autoreconf
|
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth Casson... | create #defines from identified registers, per opcode
|
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth Casson... | clarify docstring on id_regs.py
|
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth Casson... | add function identifying the registers in each emulated...
|
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth Casson... | identify instructions, plan: extract registers
|
commit | commitdiff | tree |
|
projects / riscv-isa-sim.git / search