Make -H halt the core right out of reset.
[riscv-isa-sim.git] / tests /
drwxr-xr-x   ..
-rw-r--r-- 419 debug.c
-rwxr-xr-x 721 ebreak.py
-rw-r--r-- 76 ebreak.s
-rwxr-xr-x 6366 gdbserver.py
-rw-r--r-- 1009 regs.s
-rw-r--r-- 2905 testlib.py