add hwacha exception support
[riscv-tests.git] / env / v / riscv_test.h
1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
2 #define _ENV_VIRTUAL_SINGLE_CORE_H
3
4 //-----------------------------------------------------------------------
5 // Begin Macro
6 //-----------------------------------------------------------------------
7
8 #define RVTEST_RV64U \
9 .macro init; \
10 .endm
11
12 #define RVTEST_RV64UF \
13 .macro init; \
14 fssr x0; \
15 .endm
16
17 #define RVTEST_VEC_ENABLE \
18
19 #define RVTEST_CODE_BEGIN \
20 .text; \
21 .align 13; \
22 .global userstart; \
23 userstart: \
24 init
25
26 //-----------------------------------------------------------------------
27 // End Macro
28 //-----------------------------------------------------------------------
29
30 #define RVTEST_CODE_END \
31
32 //-----------------------------------------------------------------------
33 // Pass/Fail Macro
34 //-----------------------------------------------------------------------
35
36 #define RVTEST_PASS li a0, 1; syscall;
37 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
38
39 //-----------------------------------------------------------------------
40 // Data Section Macro
41 //-----------------------------------------------------------------------
42
43 #define RVTEST_DATA_BEGIN
44 #define RVTEST_DATA_END
45
46 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
47 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
48
49 //-----------------------------------------------------------------------
50 // Supervisor mode definitions and macros
51 //-----------------------------------------------------------------------
52
53 #include "../pcr.h"
54 #include "../hwacha_xcpt.h"
55
56 #define vvcfg(nxregs, nfregs) ({ \
57 asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); })
58
59 #define vsetvl(vl) ({ long __tmp; \
60 asm volatile ("vsetvl %0,%1" : "=r"(__tmp) : "r"(vl)); })
61
62 #define vcfg(word) ({ vvcfg((word)>>12, (word)>>18); vsetvl((word)); })
63
64 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
65 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
66 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
67 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
68 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
69
70 #define fencevl() ({ \
71 asm volatile ("fence.v.l" ::: "memory"); })
72
73 #define vxcptkill() ({ \
74 asm volatile ("vxcptkill"); })
75
76 #define vxcpthold() ({ \
77 asm volatile ("vxcpthold"); })
78
79 #define venqcmd(bits, pf) ({ \
80 asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
81
82 #define venqimm1(bits, pf) ({ \
83 asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
84
85 #define venqimm2(bits, pf) ({ \
86 asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
87
88 #define venqcnt(bits, pf) ({ \
89 asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
90
91 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
92 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
93
94 #define PGSHIFT 13
95 #define PGSIZE (1 << PGSHIFT)
96
97 #define SIZEOF_TRAPFRAME_T 1336
98
99 #ifndef __ASSEMBLER__
100
101
102 typedef unsigned long pte_t;
103 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
104 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
105 #define VPN_BITS (PTIDXBITS * LEVELS)
106 #define VA_BITS (VPN_BITS + PGSHIFT)
107 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))
108
109 typedef struct
110 {
111 long gpr[32];
112 long sr;
113 long epc;
114 long badvaddr;
115 long cause;
116 long insn;
117 long vecbank;
118 long veccfg;
119 long evac[128];
120 } trapframe_t;
121 #endif
122
123 #endif