git.libre-soc.org Git - riscv-tests.git/commit

author	Yunsup Lee <yunsup@cs.berkeley.edu>
	Fri, 18 Oct 2013 02:35:34 +0000 (19:35 -0700)
committer	Yunsup Lee <yunsup@cs.berkeley.edu>
	Fri, 18 Oct 2013 02:35:34 +0000 (19:35 -0700)
commit	2f00c0c1f26a10f93f4a133bec69f4d0b95df685
tree	699ebd180e0de1076a2a511e5a2f133035dc8ca8	tree
parent	ddf8212714fcb6dc240a71bd1e1f52e02fc208b0	commit \| diff

add hwacha exception support

21 files changed:

.gitignore		diff \| blob \| history
env/hwacha_xcpt.h	[new file with mode: 0644]	blob
env/p/riscv_test.h		diff \| blob \| history
env/pcr.h		diff \| blob \| history
env/v/riscv_test.h		diff \| blob \| history
env/v/vm.c		diff \| blob \| history
isa/macros/scalar/test_macros.h		diff \| blob \| history
isa/rv64sv/Makefrag		diff \| blob \| history
isa/rv64sv/illegal_cfg_nfpr.S	[new file with mode: 0644]	blob
isa/rv64sv/illegal_cfg_nxpr.S	[new file with mode: 0644]	blob
isa/rv64sv/illegal_inst.S	[new file with mode: 0644]	blob
isa/rv64sv/illegal_tvec_cmd.S	[deleted file]	blob \| history
isa/rv64sv/illegal_tvec_regid.S		diff \| blob \| history
isa/rv64sv/illegal_vt_inst.S		diff \| blob \| history
isa/rv64sv/illegal_vt_regid.S		diff \| blob \| history
isa/rv64sv/ma_utld.S		diff \| blob \| history
isa/rv64sv/ma_utsd.S		diff \| blob \| history
isa/rv64sv/ma_vld.S		diff \| blob \| history
isa/rv64sv/ma_vsd.S		diff \| blob \| history
isa/rv64sv/ma_vt_inst.S		diff \| blob \| history
isa/rv64sv/privileged_inst.S	[new file with mode: 0644]	blob