1 #*****************************************************************************
3 #-----------------------------------------------------------------------------
5 # Test illegal tvec command trap.
8 #include "riscv_test.h"
9 #include "test_macros.h"
14 setpcr status, SR_EI # enable interrupt
17 mtpcr a3,evec # set exception handler
21 slli a4,a4,SR_IM_SHIFT
22 or a3,a3,a4 # enable IM[COP]
26 clearpcr status, SR_S # clear S bit
29 vxcptcause a3 # privileged inst
42 li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION
47 la a4, privileged_inst
51 # make sure vector unit has cleared out
100 .dword 0xdeadbeefcafebabe
101 .dword 0xdeadbeefcafebabe
102 .dword 0xdeadbeefcafebabe
103 .dword 0xdeadbeefcafebabe