add hwacha exception support
[riscv-tests.git] / isa / rv64sv / privileged_inst.S
1 #*****************************************************************************
2 # illegal_tvec_cmd.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal tvec command trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 setpcr status, SR_EI # enable interrupt
15
16 la a3,handler
17 mtpcr a3,evec # set exception handler
18
19 mfpcr a3,status
20 li a4,(1 << IRQ_COP)
21 slli a4,a4,SR_IM_SHIFT
22 or a3,a3,a4 # enable IM[COP]
23 mtpcr a3,status
24
25 setpcr status, SR_U64
26 clearpcr status, SR_S # clear S bit
27
28 privileged_inst:
29 vxcptcause a3 # privileged inst
30
31 vtcode2:
32 add x2,x2,x3
33 stop
34
35 handler:
36 vxcptkill
37
38 li x28,2
39
40 # check cause
41 vxcptcause a3
42 li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION
43 bne a3,a4,fail
44
45 # check vec irq aux
46 vxcptaux a3
47 la a4, privileged_inst
48 lw a5, 0(a4)
49 bne a3,a5,fail
50
51 # make sure vector unit has cleared out
52 vsetcfg 32,0
53 li a3,4
54 vsetvl a3,a3
55
56 la a3,src1
57 la a4,src2
58 vld vx2,a3
59 vld vx3,a4
60 lui a0,%hi(vtcode2)
61 vf %lo(vtcode2)(a0)
62 la a5,dest
63 vsd vx2,a5
64 fence
65
66 ld a1,0(a5)
67 li a2,5
68 li x28,2
69 bne a1,a2,fail
70 ld a1,8(a5)
71 li x28,3
72 bne a1,a2,fail
73 ld a1,16(a5)
74 li x28,4
75 bne a1,a2,fail
76 ld a1,24(a5)
77 li x28,5
78 bne a1,a2,fail
79
80 TEST_PASSFAIL
81
82 RVTEST_CODE_END
83
84 .data
85 RVTEST_DATA_BEGIN
86
87 TEST_DATA
88
89 src1:
90 .dword 1
91 .dword 2
92 .dword 3
93 .dword 4
94 src2:
95 .dword 4
96 .dword 3
97 .dword 2
98 .dword 1
99 dest:
100 .dword 0xdeadbeefcafebabe
101 .dword 0xdeadbeefcafebabe
102 .dword 0xdeadbeefcafebabe
103 .dword 0xdeadbeefcafebabe
104
105 RVTEST_DATA_END