isa/rv64sv/illegal_cfg_nxpr.S

   1 #*****************************************************************************
   2 # illegal_tvec_cmd.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test illegal tvec command trap.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64S
  12 RVTEST_CODE_BEGIN
  13
  14   setpcr status, SR_EI # enable interrupt
  15
  16   la a3,handler
  17   mtpcr a3,evec # set exception handler
  18
  19   mfpcr a3,status
  20   li a4,(1 << IRQ_COP)
  21   slli a4,a4,SR_IM_SHIFT
  22   or a3,a3,a4 # enable IM[COP]
  23   mtpcr a3,status
  24
  25   li a0,33
  26   vsetcfg a0
  27
  28 vtcode2:
  29   add x2,x2,x3
  30   stop
  31
  32 handler:
  33   vxcptkill
  34
  35   li x28,2
  36
  37   # check cause
  38   vxcptcause a3
  39   li a4,HWACHA_CAUSE_ILLEGAL_CFG
  40   bne a3,a4,fail
  41
  42   # check vec irq aux
  43   vxcptaux a3
  44   li a4, 0
  45   bne a3,a4,fail
  46
  47   # make sure vector unit has cleared out
  48   vsetcfg 32,0
  49   li a3,4
  50   vsetvl a3,a3
  51
  52   la a3,src1
  53   la a4,src2
  54   vld vx2,a3
  55   vld vx3,a4
  56   lui a0,%hi(vtcode2)
  57   vf %lo(vtcode2)(a0)
  58   la a5,dest
  59   vsd vx2,a5
  60   fence
  61
  62   ld a1,0(a5)
  63   li a2,5
  64   li x28,2
  65   bne a1,a2,fail
  66   ld a1,8(a5)
  67   li x28,3
  68   bne a1,a2,fail
  69   ld a1,16(a5)
  70   li x28,4
  71   bne a1,a2,fail
  72   ld a1,24(a5)
  73   li x28,5
  74   bne a1,a2,fail
  75
  76   TEST_PASSFAIL
  77
  78 RVTEST_CODE_END
  79
  80   .data
  81 RVTEST_DATA_BEGIN
  82
  83   TEST_DATA
  84
  85 src1:
  86   .dword 1
  87   .dword 2
  88   .dword 3
  89   .dword 4
  90 src2:
  91   .dword 4
  92   .dword 3
  93   .dword 2
  94   .dword 1
  95 dest:
  96   .dword 0xdeadbeefcafebabe
  97   .dword 0xdeadbeefcafebabe
  98   .dword 0xdeadbeefcafebabe
  99   .dword 0xdeadbeefcafebabe
 100
 101 RVTEST_DATA_END