isa/rv64si/ma_fetch.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_fetch.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned fetch trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sbadaddr mbadaddr
  21   #define sepc mepc
  22   #define sret mret
  23   #define stvec_handler mtvec_handler
  24 #endif
  25
  26   .option norvc
  27
  28   # Without RVC, the jalr should trap, and the handler will skip ahead.
  29   # With RVC, the jalr should not trap, and "j fail" should get skipped.
  30   li TESTNUM, 2
  31   li t1, 0
  32   la t0, 1f
  33   jalr t1, t0, 2
  34 1:
  35   .option rvc
  36   c.j 1f
  37   c.j 2f
  38   .option norvc
  39 1:
  40   j fail
  41 2:
  42
  43   // This test should pass, since JALR ignores the target LSB
  44   li TESTNUM, 3
  45   la t0, 1f
  46   jalr t1, t0, 1
  47 1:
  48   j 1f
  49   j fail
  50 1:
  51
  52   li TESTNUM, 4
  53   li t1, 0
  54   la t0, 1f
  55   jalr t1, t0, 3
  56 1:
  57   .option rvc
  58   c.j 1f
  59   c.j 2f
  60   .option norvc
  61 1:
  62   j fail
  63 2:
  64
  65   # Like test 2, but with jal instead of jalr.
  66   li TESTNUM, 5
  67   li t1, 0
  68   la t0, 1f
  69   jal t1, 2f
  70 1:
  71   .option rvc
  72   c.j 1f
  73 2:
  74   c.j 2f
  75   .option norvc
  76 1:
  77   j fail
  78 2:
  79
  80   # Like test 2, but with a taken branch instead of jalr.
  81   li TESTNUM, 6
  82   li t1, 0
  83   la t0, 1f
  84   beqz x0, 2f
  85 1:
  86   .option rvc
  87   c.j 1f
  88 2:
  89   c.j 2f
  90   .option norvc
  91 1:
  92   j fail
  93 2:
  94
  95   # Not-taken branches should not trap, even without RVC.
  96   li TESTNUM, 7
  97   bnez x0, 1f
  98   j 2f
  99   .option rvc
 100   c.j 1f
 101 1:
 102   c.j 1f
 103   .option norvc
 104 1:
 105   j fail
 106 2:
 107
 108   j pass
 109
 110   TEST_PASSFAIL
 111
 112   .align 2
 113 stvec_handler:
 114   # tests 2, 4, 5, and 6 should trap
 115   li a0, 2
 116   beq TESTNUM, a0, 1f
 117   li a0, 4
 118   beq TESTNUM, a0, 1f
 119   li a0, 5
 120   beq TESTNUM, a0, 1f
 121   li a0, 6
 122   beq TESTNUM, a0, 1f
 123   j fail
 124 1:
 125
 126   # verify that return address was not written
 127   bnez t1, fail
 128
 129   # verify trap cause
 130   li a1, CAUSE_MISALIGNED_FETCH
 131   csrr a0, scause
 132   bne a0, a1, fail
 133
 134   # verify that epc == &jalr (== t0 - 4)
 135   csrr a1, sepc
 136   addi a1, a1, 4
 137   bne t0, a1, fail
 138
 139   # verify that badaddr == 0 or badaddr == t0+2.
 140   csrr a0, sbadaddr
 141   beqz a0, 1f
 142   addi a0, a0, -2
 143   bne a0, t0, fail
 144 1:
 145
 146   addi a1, a1, 12
 147   csrw sepc, a1
 148   sret
 149
 150 RVTEST_CODE_END
 151
 152   .data
 153 RVTEST_DATA_BEGIN
 154
 155   TEST_DATA
 156
 157 RVTEST_DATA_END