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Merge branch 'master' of https://github.com/riscv/riscv-tests
author
Tim Newsome
<tim@sifive.com>
Wed, 22 Aug 2018 20:47:26 +0000
(13:47 -0700)
committer
Tim Newsome
<tim@sifive.com>
Wed, 22 Aug 2018 20:47:26 +0000
(13:47 -0700)
isa/rv64si/scall.S
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diff --git
a/isa/rv64si/scall.S
b/isa/rv64si/scall.S
index 0579806e9af0770cf7c04eb689e25ec29d055c9e..82f202a361836866ac69c4ab3e7cb392362c07d2 100644
(file)
--- a/
isa/rv64si/scall.S
+++ b/
isa/rv64si/scall.S
@@
-34,8
+34,8
@@
RVTEST_CODE_BEGIN
# Otherwise, if in S mode, then U mode must exist and we don't need to check.
li t0, MSTATUS_MPP
csrc mstatus, t0
- csrr t
1
, mstatus
- and t0, t0, t
1
+ csrr t
2
, mstatus
+ and t0, t0, t
2
beqz t0, 1f
# If U mode doesn't exist, mcause should indicate ECALL from M mode.