3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 from migen
.fhdl
import verilog
32 from riscvdefs
import *
35 class MemoryInterface
:
36 fetch_address
= Signal(32, name
="memory_interface_fetch_address") # XXX [2:]
37 fetch_data
= Signal(32, name
="memory_interface_fetch_data")
38 fetch_valid
= Signal(name
="memory_interface_fetch_valid")
39 rw_address
= Signal(32, name
="memory_interface_rw_address") # XXX [2:]
40 rw_byte_mask
= Signal(4, name
="memory_interface_rw_byte_mask")
41 rw_read_not_write
= Signal(name
="memory_interface_rw_read_not_write")
42 rw_active
= Signal(name
="memory_interface_rw_active")
43 rw_data_in
= Signal(32, name
="memory_interface_rw_data_in")
44 rw_data_out
= Signal(32, name
="memory_interface_rw_data_out")
45 rw_address_valid
= Signal(name
="memory_interface_rw_address_valid")
46 rw_wait
= Signal(name
="memory_interface_rw_wait")
53 def get_ls_misaligned(self
, ls
, funct3
, load_store_address_low_2
):
54 return Case(funct3
[:2],
55 { F3
.sb
: ls
.eq(Constant(0)),
56 F3
.sh
: ls
.eq(load_store_address_low_2
[0] != 0),
57 F3
.sw
: ls
.eq(load_store_address_low_2
[0:2] != Constant(0, 2)),
58 "default": ls
.eq(Constant(1))
62 #self.clk = ClockSignal()
63 #self.reset = ResetSignal()
64 self
.tty_write
= Signal()
65 self
.tty_write_data
= Signal(8)
66 self
.tty_write_busy
= Signal()
67 self
.switch_2
= Signal()
68 self
.switch_3
= Signal()
72 ram_size
= Constant(0x8000)
73 ram_start
= Constant(0x10000, 32)
74 reset_vector
= Signal(32)
77 reset_vector
.eq(ram_start
)
78 mtvec
.eq(ram_start
+ 0x40)
82 l
.append(Signal(32, name
="register%d" % i
))
85 #self.sync += self.registers[0].eq(0)
86 #self.sync += self.registers[1].eq(0)
88 mi
= MemoryInterface()
90 mii
= Instance("cpu_memory_interface", name
="memory_instance",
91 p_ram_size
= ram_size
,
92 p_ram_start
= ram_start
,
95 i_fetch_address
= mi
.fetch_address
,
96 o_fetch_data
= mi
.fetch_data
,
97 o_fetch_valid
= mi
.fetch_valid
,
98 i_rw_address
= mi
.rw_address
,
99 i_rw_byte_mask
= mi
.rw_byte_mask
,
100 i_rw_read_not_write
= mi
.rw_read_not_write
,
101 i_rw_active
= mi
.rw_active
,
102 i_rw_data_in
= mi
.rw_data_in
,
103 o_rw_data_out
= mi
.rw_data_out
,
104 o_rw_address_valid
= mi
.rw_address_valid
,
105 o_rw_wait
= mi
.rw_wait
,
106 o_tty_write
= self
.tty_write
,
107 o_tty_write_data
= self
.tty_write_data
,
108 i_tty_write_busy
= self
.tty_write_busy
,
109 i_switch_2
= self
.switch_2
,
110 i_switch_3
= self
.switch_3
,
111 o_led_1
= self
.led_1
,
116 fetch_act
= Signal(fetch_action
)
117 fetch_target_pc
= Signal(32)
118 fetch_output_pc
= Signal(32)
119 fetch_output_instruction
= Signal(32)
120 fetch_output_st
= Signal(fetch_output_state
)
122 fs
= Instance("CPUFetchStage", name
="fetch_stage",
125 o_memory_interface_fetch_address
= mi
.fetch_address
,
126 i_memory_interface_fetch_data
= mi
.fetch_data
,
127 i_memory_interface_fetch_valid
= mi
.fetch_valid
,
128 i_fetch_action
= fetch_act
,
129 i_target_pc
= fetch_target_pc
,
130 o_output_pc
= fetch_output_pc
,
131 o_output_instruction
= fetch_output_instruction
,
132 o_output_state
= fetch_output_st
,
133 i_reset_vector
= reset_vector
,
138 decoder_funct7
= Signal(7)
139 decoder_funct3
= Signal(3)
140 decoder_rd
= Signal(5)
141 decoder_rs1
= Signal(5)
142 decoder_rs2
= Signal(5)
143 decoder_immediate
= Signal(32)
144 decoder_opcode
= Signal(7)
145 decode_act
= Signal(decode_action
)
147 cd
= Instance("CPUDecoder", name
="decoder",
148 i_instruction
= fetch_output_instruction
,
149 o_funct7
= decoder_funct7
,
150 o_funct3
= decoder_funct3
,
154 o_immediate
= decoder_immediate
,
155 o_opcode
= decoder_opcode
,
156 o_decode_action
= decode_act
160 register_rs1
= Signal(32)
161 register_rs2
= Signal(32)
162 self
.comb
+= If(decoder_rs1
== 0,
165 register_rs1
.eq(registers
[decoder_rs1
-1]))
166 self
.comb
+= If(decoder_rs2
== 0,
169 register_rs2
.eq(registers
[decoder_rs2
-1]))
171 load_store_address
= Signal(32)
172 load_store_address_low_2
= Signal(2)
174 self
.comb
+= load_store_address
.eq(decoder_immediate
+ register_rs1
)
175 self
.comb
+= load_store_address_low_2
.eq(
176 decoder_immediate
[:2] + register_rs1
[:2])
178 load_store_misaligned
= Signal()
180 lsa
= self
.get_ls_misaligned(load_store_misaligned
, decoder_funct3
,
181 load_store_address_low_2
)
185 if __name__
== "__main__":
187 print(verilog
.convert(example
,
190 example
.tty_write_data
,
191 example
.tty_write_busy
,
200 assign memory_interface_rw_address = load_store_address[31:2];
202 wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
204 assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
206 assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
207 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
208 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
209 assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
210 assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
211 assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
213 wire [31:0] unmasked_loaded_value;
215 assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
216 ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
217 : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
218 assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
219 assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
221 wire [31:0] loaded_value;
223 assign loaded_value[7:0] = unmasked_loaded_value[7:0];
224 assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
225 assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
227 assign memory_interface_rw_active = ~reset
228 & (fetch_output_state == `fetch_output_state_valid)
229 & ~load_store_misaligned
230 & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
232 assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
234 wire [31:0] alu_a = register_rs1;
235 wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
236 wire [31:0] alu_result;
239 .funct7(decoder_funct7),
240 .funct3(decoder_funct3),
241 .opcode(decoder_opcode),
247 wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
249 assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
250 assign fetch_target_pc[0] = 0;
252 wire misaligned_jump_target = fetch_target_pc[1];
254 wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
255 wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
257 wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
259 reg [31:0] mcause = 0;
260 reg [31:0] mepc = 32'hXXXXXXXX;
261 reg [31:0] mscratch = 32'hXXXXXXXX;
263 reg mstatus_mpie = 1'bX;
265 parameter mstatus_mprv = 0;
266 parameter mstatus_tsr = 0;
267 parameter mstatus_tw = 0;
268 parameter mstatus_tvm = 0;
269 parameter mstatus_mxr = 0;
270 parameter mstatus_sum = 0;
271 parameter mstatus_xs = 0;
272 parameter mstatus_fs = 0;
273 parameter mstatus_mpp = 2'b11;
274 parameter mstatus_spp = 0;
275 parameter mstatus_spie = 0;
276 parameter mstatus_upie = 0;
277 parameter mstatus_sie = 0;
278 parameter mstatus_uie = 0;
283 parameter mie_seie = 0;
284 parameter mie_ueie = 0;
285 parameter mie_stie = 0;
286 parameter mie_utie = 0;
287 parameter mie_ssie = 0;
288 parameter mie_usie = 0;
290 task reset_to_initial;
294 mscratch = 32'hXXXXXXXX;
300 registers['h01] <= 32'hXXXXXXXX;
301 registers['h02] <= 32'hXXXXXXXX;
302 registers['h03] <= 32'hXXXXXXXX;
303 registers['h04] <= 32'hXXXXXXXX;
304 registers['h05] <= 32'hXXXXXXXX;
305 registers['h06] <= 32'hXXXXXXXX;
306 registers['h07] <= 32'hXXXXXXXX;
307 registers['h08] <= 32'hXXXXXXXX;
308 registers['h09] <= 32'hXXXXXXXX;
309 registers['h0A] <= 32'hXXXXXXXX;
310 registers['h0B] <= 32'hXXXXXXXX;
311 registers['h0C] <= 32'hXXXXXXXX;
312 registers['h0D] <= 32'hXXXXXXXX;
313 registers['h0E] <= 32'hXXXXXXXX;
314 registers['h0F] <= 32'hXXXXXXXX;
315 registers['h10] <= 32'hXXXXXXXX;
316 registers['h11] <= 32'hXXXXXXXX;
317 registers['h12] <= 32'hXXXXXXXX;
318 registers['h13] <= 32'hXXXXXXXX;
319 registers['h14] <= 32'hXXXXXXXX;
320 registers['h15] <= 32'hXXXXXXXX;
321 registers['h16] <= 32'hXXXXXXXX;
322 registers['h17] <= 32'hXXXXXXXX;
323 registers['h18] <= 32'hXXXXXXXX;
324 registers['h19] <= 32'hXXXXXXXX;
325 registers['h1A] <= 32'hXXXXXXXX;
326 registers['h1B] <= 32'hXXXXXXXX;
327 registers['h1C] <= 32'hXXXXXXXX;
328 registers['h1D] <= 32'hXXXXXXXX;
329 registers['h1E] <= 32'hXXXXXXXX;
330 registers['h1F] <= 32'hXXXXXXXX;
334 task write_register(input [4:0] register_number, input [31:0] value);
336 if(register_number != 0)
337 registers[register_number] <= value;
341 function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
344 `funct3_csrrw, `funct3_csrrwi:
345 evaluate_csr_funct3_operation = written_value;
346 `funct3_csrrs, `funct3_csrrsi:
347 evaluate_csr_funct3_operation = written_value | previous_value;
348 `funct3_csrrc, `funct3_csrrci:
349 evaluate_csr_funct3_operation = ~written_value & previous_value;
351 evaluate_csr_funct3_operation = 32'hXXXXXXXX;
356 parameter misa_a = 1'b0;
357 parameter misa_b = 1'b0;
358 parameter misa_c = 1'b0;
359 parameter misa_d = 1'b0;
360 parameter misa_e = 1'b0;
361 parameter misa_f = 1'b0;
362 parameter misa_g = 1'b0;
363 parameter misa_h = 1'b0;
364 parameter misa_i = 1'b1;
365 parameter misa_j = 1'b0;
366 parameter misa_k = 1'b0;
367 parameter misa_l = 1'b0;
368 parameter misa_m = 1'b0;
369 parameter misa_n = 1'b0;
370 parameter misa_o = 1'b0;
371 parameter misa_p = 1'b0;
372 parameter misa_q = 1'b0;
373 parameter misa_r = 1'b0;
374 parameter misa_s = 1'b0;
375 parameter misa_t = 1'b0;
376 parameter misa_u = 1'b0;
377 parameter misa_v = 1'b0;
378 parameter misa_w = 1'b0;
379 parameter misa_x = 1'b0;
380 parameter misa_y = 1'b0;
381 parameter misa_z = 1'b0;
412 parameter mvendorid = 32'b0;
413 parameter marchid = 32'b0;
414 parameter mimpid = 32'b0;
415 parameter mhartid = 32'b0;
417 function [31:0] make_mstatus(input mstatus_tsr,
423 input [1:0] mstatus_xs,
424 input [1:0] mstatus_fs,
425 input [1:0] mstatus_mpp,
434 make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
458 wire mip_meip = 0; // TODO: implement external interrupts
459 parameter mip_seip = 0;
460 parameter mip_ueip = 0;
461 wire mip_mtip = 0; // TODO: implement timer interrupts
462 parameter mip_stip = 0;
463 parameter mip_utip = 0;
464 parameter mip_msip = 0;
465 parameter mip_ssip = 0;
466 parameter mip_usip = 0;
468 wire csr_op_is_valid;
470 function `fetch_action get_fetch_action(
471 input `fetch_output_state fetch_output_state,
472 input `decode_action decode_action,
473 input load_store_misaligned,
474 input memory_interface_rw_address_valid,
475 input memory_interface_rw_wait,
477 input misaligned_jump_target,
478 input csr_op_is_valid
481 case(fetch_output_state)
482 `fetch_output_state_empty:
483 get_fetch_action = `fetch_action_default;
484 `fetch_output_state_trap:
485 get_fetch_action = `fetch_action_ack_trap;
486 `fetch_output_state_valid: begin
487 if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
488 get_fetch_action = `fetch_action_error_trap;
490 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
491 get_fetch_action = `fetch_action_noerror_trap;
493 else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
494 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
495 get_fetch_action = `fetch_action_error_trap;
497 else if(memory_interface_rw_wait) begin
498 get_fetch_action = `fetch_action_wait;
501 get_fetch_action = `fetch_action_default;
504 else if((decode_action & `decode_action_fence_i) != 0) begin
505 get_fetch_action = `fetch_action_fence;
507 else if((decode_action & `decode_action_branch) != 0) begin
508 if(branch_taken) begin
509 if(misaligned_jump_target) begin
510 get_fetch_action = `fetch_action_error_trap;
513 get_fetch_action = `fetch_action_jump;
518 get_fetch_action = `fetch_action_default;
521 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
522 if(misaligned_jump_target) begin
523 get_fetch_action = `fetch_action_error_trap;
526 get_fetch_action = `fetch_action_jump;
529 else if((decode_action & `decode_action_csr) != 0) begin
531 get_fetch_action = `fetch_action_default;
533 get_fetch_action = `fetch_action_error_trap;
536 get_fetch_action = `fetch_action_default;
540 get_fetch_action = 32'hXXXXXXXX;
545 assign fetch_action = get_fetch_action(
548 load_store_misaligned,
549 memory_interface_rw_address_valid,
550 memory_interface_rw_wait,
552 misaligned_jump_target,
558 mstatus_mpie = mstatus_mie;
560 mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
561 if(fetch_action == `fetch_action_ack_trap) begin
562 mcause = `cause_instruction_access_fault;
564 else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
565 mcause = `cause_illegal_instruction;
567 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
568 mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
570 else if((decode_action & `decode_action_load) != 0) begin
571 if(load_store_misaligned)
572 mcause = `cause_load_address_misaligned;
574 mcause = `cause_load_access_fault;
576 else if((decode_action & `decode_action_store) != 0) begin
577 if(load_store_misaligned)
578 mcause = `cause_store_amo_address_misaligned;
580 mcause = `cause_store_amo_access_fault;
582 else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
583 mcause = `cause_instruction_address_misaligned;
586 mcause = `cause_illegal_instruction;
591 wire [11:0] csr_number = decoder_immediate;
592 wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
593 wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
594 wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
596 function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
627 get_csr_op_is_valid = 0;
638 get_csr_op_is_valid = ~csr_writes;
647 get_csr_op_is_valid = 1;
654 // TODO: CSRs not implemented yet
655 get_csr_op_is_valid = 0;
660 assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
662 wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
663 wire [63:0] time_counter = 0; // TODO: implement time_counter
664 wire [63:0] instret_counter = 0; // TODO: implement instret_counter
666 always @(posedge clk) begin:main_block
671 case(fetch_output_state)
672 `fetch_output_state_empty: begin
674 `fetch_output_state_trap: begin
677 `fetch_output_state_valid: begin:valid
678 if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
681 else if((decode_action & `decode_action_load) != 0) begin
682 if(~memory_interface_rw_wait)
683 write_register(decoder_rd, loaded_value);
685 else if((decode_action & `decode_action_op_op_imm) != 0) begin
686 write_register(decoder_rd, alu_result);
688 else if((decode_action & `decode_action_lui_auipc) != 0) begin
689 write_register(decoder_rd, lui_auipc_result);
691 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
692 write_register(decoder_rd, fetch_output_pc + 4);
694 else if((decode_action & `decode_action_csr) != 0) begin:csr
695 reg [31:0] csr_output_value;
696 reg [31:0] csr_written_value;
697 csr_output_value = 32'hXXXXXXXX;
698 csr_written_value = 32'hXXXXXXXX;
701 csr_output_value = cycle_counter[31:0];
704 csr_output_value = time_counter[31:0];
707 csr_output_value = instret_counter[31:0];
710 csr_output_value = cycle_counter[63:32];
713 csr_output_value = time_counter[63:32];
716 csr_output_value = instret_counter[63:32];
718 `csr_mvendorid: begin
719 csr_output_value = mvendorid;
722 csr_output_value = marchid;
725 csr_output_value = mimpid;
728 csr_output_value = mhartid;
731 csr_output_value = misa;
734 csr_output_value = make_mstatus(mstatus_tsr,
750 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
752 mstatus_mpie = csr_written_value[7];
753 mstatus_mie = csr_written_value[3];
757 csr_output_value = 0;
758 csr_output_value[11] = mie_meie;
759 csr_output_value[9] = mie_seie;
760 csr_output_value[8] = mie_ueie;
761 csr_output_value[7] = mie_mtie;
762 csr_output_value[5] = mie_stie;
763 csr_output_value[4] = mie_utie;
764 csr_output_value[3] = mie_msie;
765 csr_output_value[1] = mie_ssie;
766 csr_output_value[0] = mie_usie;
767 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
769 mie_meie = csr_written_value[11];
770 mie_mtie = csr_written_value[7];
771 mie_msie = csr_written_value[3];
775 csr_output_value = mtvec;
778 csr_output_value = mscratch;
779 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
781 mscratch = csr_written_value;
784 csr_output_value = mepc;
785 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
787 mepc = csr_written_value;
790 csr_output_value = mcause;
791 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
793 mcause = csr_written_value;
796 csr_output_value = 0;
797 csr_output_value[11] = mip_meip;
798 csr_output_value[9] = mip_seip;
799 csr_output_value[8] = mip_ueip;
800 csr_output_value[7] = mip_mtip;
801 csr_output_value[5] = mip_stip;
802 csr_output_value[4] = mip_utip;
803 csr_output_value[3] = mip_msip;
804 csr_output_value[1] = mip_ssip;
805 csr_output_value[0] = mip_usip;
809 write_register(decoder_rd, csr_output_value);
811 else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin