cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31 from migen.fhdl.structure import _Operator
  32
  33 from riscvdefs import *
  34 from cpudefs import *
  35
  36 class MemoryInterface:
  37     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  38     fetch_data = Signal(32, name="memory_interface_fetch_data")
  39     fetch_valid = Signal(name="memory_interface_fetch_valid")
  40     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  41     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  42     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  43     rw_active = Signal(name="memory_interface_rw_active")
  44     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  45     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  46     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  47     rw_wait = Signal(name="memory_interface_rw_wait")
  48
  49
  50 class Decoder:
  51     funct7 = Signal(7, name="decoder_funct7")
  52     funct3 = Signal(3, name="decoder_funct3")
  53     rd = Signal(5, name="decoder_rd")
  54     rs1 = Signal(5, name="decoder_rs1")
  55     rs2 = Signal(5, name="decoder_rs2")
  56     immediate = Signal(32, name="decoder_immediate")
  57     opcode = Signal(7, name="decoder_opcode")
  58     act = Signal(decode_action, name="decoder_action")
  59
  60 class MStatus:
  61     def __init__(self, comb):
  62         self.comb = comb
  63         self.mpie = Signal(name="mstatus_mpie")
  64         self.mie = Signal(name="mstatus_mie")
  65         self.mprv = Signal(name="mstatus_mprv")
  66         self.tsr = Signal(name="mstatus_tsr")
  67         self.tw = Signal(name="mstatus_tw")
  68         self.tvm = Signal(name="mstatus_tvm")
  69         self.mxr = Signal(name="mstatus_mxr")
  70         self._sum = Signal(name="mstatus_sum")
  71         self.xs = Signal(name="mstatus_xs")
  72         self.fs = Signal(name="mstatus_fs")
  73         self.mpp = Signal(2, name="mstatus_mpp")
  74         self.spp = Signal(name="mstatus_spp")
  75         self.spie = Signal(name="mstatus_spie")
  76         self.upie = Signal(name="mstatus_upie")
  77         self.sie = Signal(name="mstatus_sie")
  78         self.uie = Signal(name="mstatus_uie")
  79
  80         for n in dir(self):
  81             if n in ['mpp', 'comb'] or n.startswith("_"):
  82                 continue
  83             self.comb += getattr(self, n).eq(0x0)
  84         self.comb += self.mpp.eq(0b11)
  85
  86
  87 class CPU(Module):
  88     """
  89     """
  90
  91     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
  92         return Case(funct3[:2],
  93                 { F3.sb: ls.eq(Constant(0)),
  94                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
  95                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
  96                   "default": ls.eq(Constant(1))
  97                 })
  98
  99     def get_lsbm(self, dc):
 100         return Cat(Constant(1),
 101                    Mux((dc.funct3[1] | dc.funct3[0]),
 102                        Constant(1), Constant(0)),
 103                    Mux((dc.funct3[1]),
 104                        Constant(0b11, 2), Constant(0, 2)))
 105
 106     def __init__(self):
 107         self.clk = ClockSignal()
 108         self.reset = ResetSignal()
 109         self.tty_write = Signal()
 110         self.tty_write_data = Signal(8)
 111         self.tty_write_busy = Signal()
 112         self.switch_2 = Signal()
 113         self.switch_3 = Signal()
 114         self.led_1 = Signal()
 115         self.led_3 = Signal()
 116
 117         ram_size = Constant(0x8000)
 118         ram_start = Constant(0x10000, 32)
 119         reset_vector = Signal(32)
 120         mtvec = Signal(32)
 121
 122         reset_vector.eq(ram_start)
 123         mtvec.eq(ram_start + 0x40)
 124
 125         l = []
 126         for i in range(31):
 127             l.append(Signal(32, name="register%d" % i))
 128         registers = Array(l)
 129
 130         mi = MemoryInterface()
 131
 132         mii = Instance("cpu_memory_interface", name="memory_instance",
 133                     p_ram_size = ram_size,
 134                     p_ram_start = ram_start,
 135                     i_clk=ClockSignal(),
 136                     i_rst=ResetSignal(),
 137                     i_fetch_address = mi.fetch_address,
 138                     o_fetch_data = mi.fetch_data,
 139                     o_fetch_valid = mi.fetch_valid,
 140                     i_rw_address = mi.rw_address,
 141                     i_rw_byte_mask = mi.rw_byte_mask,
 142                     i_rw_read_not_write = mi.rw_read_not_write,
 143                     i_rw_active = mi.rw_active,
 144                     i_rw_data_in = mi.rw_data_in,
 145                     o_rw_data_out = mi.rw_data_out,
 146                     o_rw_address_valid = mi.rw_address_valid,
 147                     o_rw_wait = mi.rw_wait,
 148                     o_tty_write = self.tty_write,
 149                     o_tty_write_data = self.tty_write_data,
 150                     i_tty_write_busy = self.tty_write_busy,
 151                     i_switch_2 = self.switch_2,
 152                     i_switch_3 = self.switch_3,
 153                     o_led_1 = self.led_1,
 154                     o_led_3 = self.led_3
 155                   )
 156         self.specials += mii
 157
 158         fetch_act = Signal(fetch_action)
 159         fetch_target_pc = Signal(32)
 160         fetch_output_pc = Signal(32)
 161         fetch_output_instruction = Signal(32)
 162         fetch_output_st = Signal(fetch_output_state)
 163
 164         fs = Instance("CPUFetchStage", name="fetch_stage",
 165             i_clk=ClockSignal(),
 166             i_rst=ResetSignal(),
 167             o_memory_interface_fetch_address = mi.fetch_address,
 168             i_memory_interface_fetch_data = mi.fetch_data,
 169             i_memory_interface_fetch_valid = mi.fetch_valid,
 170             i_fetch_action = fetch_act,
 171             i_target_pc = fetch_target_pc,
 172             o_output_pc = fetch_output_pc,
 173             o_output_instruction = fetch_output_instruction,
 174             o_output_state = fetch_output_st,
 175             i_reset_vector = reset_vector,
 176             i_mtvec = mtvec,
 177         )
 178         self.specials += fs
 179
 180         dc = Decoder()
 181
 182         cd = Instance("CPUDecoder", name="decoder",
 183             i_instruction = fetch_output_instruction,
 184             o_funct7 = dc.funct7,
 185             o_funct3 = dc.funct3,
 186             o_rd = dc.rd,
 187             o_rs1 = dc.rs1,
 188             o_rs2 = dc.rs2,
 189             o_immediate = dc.immediate,
 190             o_opcode = dc.opcode,
 191             o_decode_action = dc.act
 192         )
 193         self.specials += cd
 194
 195         register_rs1 = Signal(32)
 196         register_rs2 = Signal(32)
 197         self.comb += If(dc.rs1 == 0,
 198                         register_rs1.eq(0)
 199                      ).Else(
 200                         register_rs1.eq(registers[dc.rs1-1]))
 201         self.comb += If(dc.rs2 == 0,
 202                         register_rs2.eq(0)
 203                      ).Else(
 204                         register_rs2.eq(registers[dc.rs2-1]))
 205
 206         load_store_address = Signal(32)
 207         load_store_address_low_2 = Signal(2)
 208
 209         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 210         self.comb += load_store_address_low_2.eq(
 211                             dc.immediate[:2] + register_rs1[:2])
 212
 213         load_store_misaligned = Signal()
 214
 215         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 216                                      load_store_address_low_2)
 217         self.comb += lsa
 218
 219         # XXX rwaddr not 31:2 any more
 220         self.comb += mi.rw_address.eq(load_store_address[2:])
 221
 222         unshifted_load_store_byte_mask = Signal(4)
 223
 224         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 225
 226         # XXX yuck.  this will cause migen simulation to fail
 227         # (however conversion to verilog works)
 228         self.comb += mi.rw_byte_mask.eq(
 229                 _Operator("<<", [unshifted_load_store_byte_mask,
 230                                         load_store_address_low_2]))
 231
 232         # XXX not obvious
 233         b3 = Mux(load_store_address_low_2[1],
 234                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 235                                                   register_rs2[8:16]),
 236                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 237                                                   register_rs2[24:32]))
 238         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 239                                               register_rs2[16:24])
 240         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 241                                               register_rs2[8:16])
 242         b0 = register_rs2[0:8]
 243
 244         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 245
 246         # XXX not obvious
 247         unmasked_loaded_value = Signal(32)
 248
 249         b0 = Mux(load_store_address_low_2[1],
 250                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 251                                                   mi.rw_data_out[16:24]),
 252                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 253                                                   mi.rw_data_out[0:8]))
 254         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 255                                               mi.rw_data_out[8:16])
 256         b23 = mi.rw_data_out[16:32]
 257
 258         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 259
 260         # XXX not obvious
 261         loaded_value = Signal(32)
 262
 263         b0 = unmasked_loaded_value[0:8]
 264         b1 = Mux(dc.funct3[0:2] == 0,
 265                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 266                 unmasked_loaded_value[8:16])
 267         b2 = Mux(dc.funct3[1] == 0,
 268                 Replicate(~dc.funct3[2] &
 269                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 270                                                   unmasked_loaded_value[7]),
 271                           16),
 272                 unmasked_loaded_value[16:32])
 273
 274         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 275
 276         self.comb += mi.rw_active.eq(~self.reset
 277                         & (fetch_output_st == fetch_output_state_valid)
 278                         & ~load_store_misaligned
 279                         & ((dc.act & (DA.load | DA.store)) != 0))
 280
 281         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 282
 283         # alu
 284         alu_a = Signal(32)
 285         alu_b = Signal(32)
 286         alu_result = Signal(32)
 287
 288         self.comb += alu_a.eq(register_rs1)
 289         self.comb += alu_b.eq(Mux(dc.opcode[5],
 290                                   register_rs2,
 291                                   dc.immediate))
 292
 293         ali = Instance("cpu_alu", name="alu",
 294             i_funct7 = dc.funct7,
 295             i_funct3 = dc.funct3,
 296             i_opcode = dc.opcode,
 297             i_a = alu_a,
 298             i_b = alu_b,
 299             o_result = alu_result
 300         )
 301         self.specials += ali
 302
 303         lui_auipc_result = Signal(32)
 304         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 305                                              dc.immediate,
 306                                              dc.immediate + fetch_output_pc))
 307
 308         self.comb += fetch_target_pc.eq(Cat(0,
 309                     Mux(dc.opcode != OP.jalr,
 310                                 fetch_output_pc[1:32],
 311                                 register_rs1[1:32] + dc.immediate[1:32])))
 312
 313         misaligned_jump_target = Signal()
 314         self.comb += misaligned_jump_target.eq(fetch_target_pc[1])
 315
 316         branch_arg_a = Signal(32)
 317         branch_arg_b = Signal(32)
 318         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 319                                           register_rs1[31] ^ ~dc.funct3[1]))
 320         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 321                                           register_rs2[31] ^ ~dc.funct3[1]))
 322
 323         branch_taken = Signal()
 324         self.comb += branch_taken.eq(dc.funct3[0] ^
 325                                      Mux(dc.funct3[2],
 326                                          branch_arg_a < branch_arg_b,
 327                                          branch_arg_a == branch_arg_b))
 328
 329         mcause = Signal(32)
 330         mepc = Signal(32)
 331         mscratch = Signal(32)
 332         self.comb += mcause.eq(0)
 333         self.comb += mepc.eq(0) # 32'hXXXXXXXX;
 334         self.comb += mscratch.eq(0) # 32'hXXXXXXXX;
 335
 336         mstatus = MStatus(self.comb)
 337
 338 if __name__ == "__main__":
 339     example = CPU()
 340     print(verilog.convert(example,
 341          {
 342            example.tty_write,
 343            example.tty_write_data,
 344            example.tty_write_busy,
 345            example.switch_2,
 346            example.switch_3,
 347            example.led_1,
 348            example.led_3,
 349            }))
 350
 351 """
 352
 353     reg mie_meie = 1'bX;
 354     reg mie_mtie = 1'bX;
 355     reg mie_msie = 1'bX;
 356     parameter mie_seie = 0;
 357     parameter mie_ueie = 0;
 358     parameter mie_stie = 0;
 359     parameter mie_utie = 0;
 360     parameter mie_ssie = 0;
 361     parameter mie_usie = 0;
 362
 363     task reset_to_initial;
 364     begin
 365         mcause = 0;
 366         mepc = 32'hXXXXXXXX;
 367         mscratch = 32'hXXXXXXXX;
 368         mstatus_mie = 0;
 369         mstatus_mpie = 1'bX;
 370         mie_meie = 1'bX;
 371         mie_mtie = 1'bX;
 372         mie_msie = 1'bX;
 373         registers['h01] <= 32'hXXXXXXXX;
 374         registers['h02] <= 32'hXXXXXXXX;
 375         registers['h03] <= 32'hXXXXXXXX;
 376         registers['h04] <= 32'hXXXXXXXX;
 377         registers['h05] <= 32'hXXXXXXXX;
 378         registers['h06] <= 32'hXXXXXXXX;
 379         registers['h07] <= 32'hXXXXXXXX;
 380         registers['h08] <= 32'hXXXXXXXX;
 381         registers['h09] <= 32'hXXXXXXXX;
 382         registers['h0A] <= 32'hXXXXXXXX;
 383         registers['h0B] <= 32'hXXXXXXXX;
 384         registers['h0C] <= 32'hXXXXXXXX;
 385         registers['h0D] <= 32'hXXXXXXXX;
 386         registers['h0E] <= 32'hXXXXXXXX;
 387         registers['h0F] <= 32'hXXXXXXXX;
 388         registers['h10] <= 32'hXXXXXXXX;
 389         registers['h11] <= 32'hXXXXXXXX;
 390         registers['h12] <= 32'hXXXXXXXX;
 391         registers['h13] <= 32'hXXXXXXXX;
 392         registers['h14] <= 32'hXXXXXXXX;
 393         registers['h15] <= 32'hXXXXXXXX;
 394         registers['h16] <= 32'hXXXXXXXX;
 395         registers['h17] <= 32'hXXXXXXXX;
 396         registers['h18] <= 32'hXXXXXXXX;
 397         registers['h19] <= 32'hXXXXXXXX;
 398         registers['h1A] <= 32'hXXXXXXXX;
 399         registers['h1B] <= 32'hXXXXXXXX;
 400         registers['h1C] <= 32'hXXXXXXXX;
 401         registers['h1D] <= 32'hXXXXXXXX;
 402         registers['h1E] <= 32'hXXXXXXXX;
 403         registers['h1F] <= 32'hXXXXXXXX;
 404     end
 405     endtask
 406
 407     task write_register(input [4:0] register_number, input [31:0] value);
 408     begin
 409         if(register_number != 0)
 410             registers[register_number] <= value;
 411     end
 412     endtask
 413
 414     function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
 415     begin
 416         case(funct3)
 417         `funct3_csrrw, `funct3_csrrwi:
 418             evaluate_csr_funct3_operation = written_value;
 419         `funct3_csrrs, `funct3_csrrsi:
 420             evaluate_csr_funct3_operation = written_value | previous_value;
 421         `funct3_csrrc, `funct3_csrrci:
 422             evaluate_csr_funct3_operation = ~written_value & previous_value;
 423         default:
 424             evaluate_csr_funct3_operation = 32'hXXXXXXXX;
 425         endcase
 426     end
 427     endfunction
 428
 429     parameter misa_a = 1'b0;
 430     parameter misa_b = 1'b0;
 431     parameter misa_c = 1'b0;
 432     parameter misa_d = 1'b0;
 433     parameter misa_e = 1'b0;
 434     parameter misa_f = 1'b0;
 435     parameter misa_g = 1'b0;
 436     parameter misa_h = 1'b0;
 437     parameter misa_i = 1'b1;
 438     parameter misa_j = 1'b0;
 439     parameter misa_k = 1'b0;
 440     parameter misa_l = 1'b0;
 441     parameter misa_m = 1'b0;
 442     parameter misa_n = 1'b0;
 443     parameter misa_o = 1'b0;
 444     parameter misa_p = 1'b0;
 445     parameter misa_q = 1'b0;
 446     parameter misa_r = 1'b0;
 447     parameter misa_s = 1'b0;
 448     parameter misa_t = 1'b0;
 449     parameter misa_u = 1'b0;
 450     parameter misa_v = 1'b0;
 451     parameter misa_w = 1'b0;
 452     parameter misa_x = 1'b0;
 453     parameter misa_y = 1'b0;
 454     parameter misa_z = 1'b0;
 455     parameter misa = {
 456         2'b01,
 457         4'b0,
 458         misa_z,
 459         misa_y,
 460         misa_x,
 461         misa_w,
 462         misa_v,
 463         misa_u,
 464         misa_t,
 465         misa_s,
 466         misa_r,
 467         misa_q,
 468         misa_p,
 469         misa_o,
 470         misa_n,
 471         misa_m,
 472         misa_l,
 473         misa_k,
 474         misa_j,
 475         misa_i,
 476         misa_h,
 477         misa_g,
 478         misa_f,
 479         misa_e,
 480         misa_d,
 481         misa_c,
 482         misa_b,
 483         misa_a};
 484
 485     parameter mvendorid = 32'b0;
 486     parameter marchid = 32'b0;
 487     parameter mimpid = 32'b0;
 488     parameter mhartid = 32'b0;
 489
 490     function [31:0] make_mstatus(input mstatus_tsr,
 491         input mstatus_tw,
 492         input mstatus_tvm,
 493         input mstatus_mxr,
 494         input mstatus_sum,
 495         input mstatus_mprv,
 496         input [1:0] mstatus_xs,
 497         input [1:0] mstatus_fs,
 498         input [1:0] mstatus_mpp,
 499         input mstatus_spp,
 500         input mstatus_mpie,
 501         input mstatus_spie,
 502         input mstatus_upie,
 503         input mstatus_mie,
 504         input mstatus_sie,
 505         input mstatus_uie);
 506     begin
 507         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 508             8'b0,
 509             mstatus_tsr,
 510             mstatus_tw,
 511             mstatus_tvm,
 512             mstatus_mxr,
 513             mstatus_sum,
 514             mstatus_mprv,
 515             mstatus_xs,
 516             mstatus_fs,
 517             mstatus_mpp,
 518             2'b0,
 519             mstatus_spp,
 520             mstatus_mpie,
 521             1'b0,
 522             mstatus_spie,
 523             mstatus_upie,
 524             mstatus_mie,
 525             1'b0,
 526             mstatus_sie,
 527             mstatus_uie};
 528     end
 529     endfunction
 530
 531     wire mip_meip = 0; // TODO: implement external interrupts
 532     parameter mip_seip = 0;
 533     parameter mip_ueip = 0;
 534     wire mip_mtip = 0; // TODO: implement timer interrupts
 535     parameter mip_stip = 0;
 536     parameter mip_utip = 0;
 537     parameter mip_msip = 0;
 538     parameter mip_ssip = 0;
 539     parameter mip_usip = 0;
 540
 541     wire csr_op_is_valid;
 542
 543     function `fetch_action get_fetch_action(
 544         input `fetch_output_state fetch_output_state,
 545         input `decode_action decode_action,
 546         input load_store_misaligned,
 547         input memory_interface_rw_address_valid,
 548         input memory_interface_rw_wait,
 549         input branch_taken,
 550         input misaligned_jump_target,
 551         input csr_op_is_valid
 552         );
 553     begin
 554         case(fetch_output_state)
 555         `fetch_output_state_empty:
 556             get_fetch_action = `fetch_action_default;
 557         `fetch_output_state_trap:
 558             get_fetch_action = `fetch_action_ack_trap;
 559         `fetch_output_state_valid: begin
 560             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 561                 get_fetch_action = `fetch_action_error_trap;
 562             end
 563             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 564                 get_fetch_action = `fetch_action_noerror_trap;
 565             end
 566             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 567                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 568                     get_fetch_action = `fetch_action_error_trap;
 569                 end
 570                 else if(memory_interface_rw_wait) begin
 571                     get_fetch_action = `fetch_action_wait;
 572                 end
 573                 else begin
 574                     get_fetch_action = `fetch_action_default;
 575                 end
 576             end
 577             else if((decode_action & `decode_action_fence_i) != 0) begin
 578                 get_fetch_action = `fetch_action_fence;
 579             end
 580             else if((decode_action & `decode_action_branch) != 0) begin
 581                 if(branch_taken) begin
 582                     if(misaligned_jump_target) begin
 583                         get_fetch_action = `fetch_action_error_trap;
 584                     end
 585                     else begin
 586                         get_fetch_action = `fetch_action_jump;
 587                     end
 588                 end
 589                 else
 590                 begin
 591                     get_fetch_action = `fetch_action_default;
 592                 end
 593             end
 594             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 595                 if(misaligned_jump_target) begin
 596                     get_fetch_action = `fetch_action_error_trap;
 597                 end
 598                 else begin
 599                     get_fetch_action = `fetch_action_jump;
 600                 end
 601             end
 602             else if((decode_action & `decode_action_csr) != 0) begin
 603                 if(csr_op_is_valid)
 604                     get_fetch_action = `fetch_action_default;
 605                 else
 606                     get_fetch_action = `fetch_action_error_trap;
 607             end
 608             else begin
 609                 get_fetch_action = `fetch_action_default;
 610             end
 611         end
 612         default:
 613             get_fetch_action = 32'hXXXXXXXX;
 614         endcase
 615     end
 616     endfunction
 617
 618     assign fetch_action = get_fetch_action(
 619         fetch_output_state,
 620         decode_action,
 621         load_store_misaligned,
 622         memory_interface_rw_address_valid,
 623         memory_interface_rw_wait,
 624         branch_taken,
 625         misaligned_jump_target,
 626         csr_op_is_valid
 627         );
 628
 629     task handle_trap;
 630     begin
 631         mstatus_mpie = mstatus_mie;
 632         mstatus_mie = 0;
 633         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 634         if(fetch_action == `fetch_action_ack_trap) begin
 635             mcause = `cause_instruction_access_fault;
 636         end
 637         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 638             mcause = `cause_illegal_instruction;
 639         end
 640         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 641             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 642         end
 643         else if((decode_action & `decode_action_load) != 0) begin
 644             if(load_store_misaligned)
 645                 mcause = `cause_load_address_misaligned;
 646             else
 647                 mcause = `cause_load_access_fault;
 648         end
 649         else if((decode_action & `decode_action_store) != 0) begin
 650             if(load_store_misaligned)
 651                 mcause = `cause_store_amo_address_misaligned;
 652             else
 653                 mcause = `cause_store_amo_access_fault;
 654         end
 655         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 656             mcause = `cause_instruction_address_misaligned;
 657         end
 658         else begin
 659             mcause = `cause_illegal_instruction;
 660         end
 661     end
 662     endtask
 663
 664     wire [11:0] csr_number = decoder_immediate;
 665     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 666     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 667     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 668
 669     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 670     begin
 671         case(csr_number)
 672         `csr_ustatus,
 673         `csr_fflags,
 674         `csr_frm,
 675         `csr_fcsr,
 676         `csr_uie,
 677         `csr_utvec,
 678         `csr_uscratch,
 679         `csr_uepc,
 680         `csr_ucause,
 681         `csr_utval,
 682         `csr_uip,
 683         `csr_sstatus,
 684         `csr_sedeleg,
 685         `csr_sideleg,
 686         `csr_sie,
 687         `csr_stvec,
 688         `csr_scounteren,
 689         `csr_sscratch,
 690         `csr_sepc,
 691         `csr_scause,
 692         `csr_stval,
 693         `csr_sip,
 694         `csr_satp,
 695         `csr_medeleg,
 696         `csr_mideleg,
 697         `csr_dcsr,
 698         `csr_dpc,
 699         `csr_dscratch:
 700             get_csr_op_is_valid = 0;
 701         `csr_cycle,
 702         `csr_time,
 703         `csr_instret,
 704         `csr_cycleh,
 705         `csr_timeh,
 706         `csr_instreth,
 707         `csr_mvendorid,
 708         `csr_marchid,
 709         `csr_mimpid,
 710         `csr_mhartid:
 711             get_csr_op_is_valid = ~csr_writes;
 712         `csr_misa,
 713         `csr_mstatus,
 714         `csr_mie,
 715         `csr_mtvec,
 716         `csr_mscratch,
 717         `csr_mepc,
 718         `csr_mcause,
 719         `csr_mip:
 720             get_csr_op_is_valid = 1;
 721         `csr_mcounteren,
 722         `csr_mtval,
 723         `csr_mcycle,
 724         `csr_minstret,
 725         `csr_mcycleh,
 726         `csr_minstreth:
 727             // TODO: CSRs not implemented yet
 728             get_csr_op_is_valid = 0;
 729         endcase
 730     end
 731     endfunction
 732
 733     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 734
 735     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 736     wire [63:0] time_counter = 0; // TODO: implement time_counter
 737     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 738
 739     always @(posedge clk) begin:main_block
 740         if(reset) begin
 741             reset_to_initial();
 742             disable main_block;
 743         end
 744         case(fetch_output_state)
 745         `fetch_output_state_empty: begin
 746         end
 747         `fetch_output_state_trap: begin
 748             handle_trap();
 749         end
 750         `fetch_output_state_valid: begin:valid
 751             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 752                 handle_trap();
 753             end
 754             else if((decode_action & `decode_action_load) != 0) begin
 755                 if(~memory_interface_rw_wait)
 756                     write_register(decoder_rd, loaded_value);
 757             end
 758             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 759                 write_register(decoder_rd, alu_result);
 760             end
 761             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 762                 write_register(decoder_rd, lui_auipc_result);
 763             end
 764             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 765                 write_register(decoder_rd, fetch_output_pc + 4);
 766             end
 767             else if((decode_action & `decode_action_csr) != 0) begin:csr
 768                 reg [31:0] csr_output_value;
 769                 reg [31:0] csr_written_value;
 770                 csr_output_value = 32'hXXXXXXXX;
 771                 csr_written_value = 32'hXXXXXXXX;
 772                 case(csr_number)
 773                 `csr_cycle: begin
 774                     csr_output_value = cycle_counter[31:0];
 775                 end
 776                 `csr_time: begin
 777                     csr_output_value = time_counter[31:0];
 778                 end
 779                 `csr_instret: begin
 780                     csr_output_value = instret_counter[31:0];
 781                 end
 782                 `csr_cycleh: begin
 783                     csr_output_value = cycle_counter[63:32];
 784                 end
 785                 `csr_timeh: begin
 786                     csr_output_value = time_counter[63:32];
 787                 end
 788                 `csr_instreth: begin
 789                     csr_output_value = instret_counter[63:32];
 790                 end
 791                 `csr_mvendorid: begin
 792                     csr_output_value = mvendorid;
 793                 end
 794                 `csr_marchid: begin
 795                     csr_output_value = marchid;
 796                 end
 797                 `csr_mimpid: begin
 798                     csr_output_value = mimpid;
 799                 end
 800                 `csr_mhartid: begin
 801                     csr_output_value = mhartid;
 802                 end
 803                 `csr_misa: begin
 804                     csr_output_value = misa;
 805                 end
 806                 `csr_mstatus: begin
 807                     csr_output_value = make_mstatus(mstatus_tsr,
 808                                                     mstatus_tw,
 809                                                     mstatus_tvm,
 810                                                     mstatus_mxr,
 811                                                     mstatus_sum,
 812                                                     mstatus_mprv,
 813                                                     mstatus_xs,
 814                                                     mstatus_fs,
 815                                                     mstatus_mpp,
 816                                                     mstatus_spp,
 817                                                     mstatus_mpie,
 818                                                     mstatus_spie,
 819                                                     mstatus_upie,
 820                                                     mstatus_mie,
 821                                                     mstatus_sie,
 822                                                     mstatus_uie);
 823                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 824                     if(csr_writes) begin
 825                         mstatus_mpie = csr_written_value[7];
 826                         mstatus_mie = csr_written_value[3];
 827                     end
 828                 end
 829                 `csr_mie: begin
 830                     csr_output_value = 0;
 831                     csr_output_value[11] = mie_meie;
 832                     csr_output_value[9] = mie_seie;
 833                     csr_output_value[8] = mie_ueie;
 834                     csr_output_value[7] = mie_mtie;
 835                     csr_output_value[5] = mie_stie;
 836                     csr_output_value[4] = mie_utie;
 837                     csr_output_value[3] = mie_msie;
 838                     csr_output_value[1] = mie_ssie;
 839                     csr_output_value[0] = mie_usie;
 840                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 841                     if(csr_writes) begin
 842                         mie_meie = csr_written_value[11];
 843                         mie_mtie = csr_written_value[7];
 844                         mie_msie = csr_written_value[3];
 845                     end
 846                 end
 847                 `csr_mtvec: begin
 848                     csr_output_value = mtvec;
 849                 end
 850                 `csr_mscratch: begin
 851                     csr_output_value = mscratch;
 852                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 853                     if(csr_writes)
 854                         mscratch = csr_written_value;
 855                 end
 856                 `csr_mepc: begin
 857                     csr_output_value = mepc;
 858                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 859                     if(csr_writes)
 860                         mepc = csr_written_value;
 861                 end
 862                 `csr_mcause: begin
 863                     csr_output_value = mcause;
 864                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 865                     if(csr_writes)
 866                         mcause = csr_written_value;
 867                 end
 868                 `csr_mip: begin
 869                     csr_output_value = 0;
 870                     csr_output_value[11] = mip_meip;
 871                     csr_output_value[9] = mip_seip;
 872                     csr_output_value[8] = mip_ueip;
 873                     csr_output_value[7] = mip_mtip;
 874                     csr_output_value[5] = mip_stip;
 875                     csr_output_value[4] = mip_utip;
 876                     csr_output_value[3] = mip_msip;
 877                     csr_output_value[1] = mip_ssip;
 878                     csr_output_value[0] = mip_usip;
 879                 end
 880                 endcase
 881                 if(csr_reads)
 882                     write_register(decoder_rd, csr_output_value);
 883             end
 884             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 885                 // do nothing
 886             end
 887         end
 888         endcase
 889     end
 890
 891 endmodule
 892 """
 893