cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61
  62 class MStatus:
  63     def __init__(self, comb, sync):
  64         self.comb = comb
  65         self.sync = sync
  66         self.mpie = Signal(name="mstatus_mpie")
  67         self.mie = Signal(name="mstatus_mie")
  68         self.mstatus = Signal(32, name="mstatus")
  69
  70         self.sync += self.mie.eq(0)
  71         self.sync += self.mpie.eq(0)
  72         self.sync += self.mstatus.eq(0)
  73
  74
  75 class MIE:
  76     def __init__(self, comb, sync):
  77         self.comb = comb
  78         self.sync = sync
  79         self.meie = Signal(name="mie_meie")
  80         self.mtie = Signal(name="mie_mtie")
  81         self.msie = Signal(name="mie_msie")
  82         self.seie = Signal(name="mie_seie")
  83         self.ueie = Signal(name="mie_ueie")
  84         self.stie = Signal(name="mie_stie")
  85         self.utie = Signal(name="mie_utie")
  86         self.ssie = Signal(name="mie_ssie")
  87         self.usie = Signal(name="mie_usie")
  88
  89         for n in dir(self):
  90             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
  91                 continue
  92             self.comb += getattr(self, n).eq(0x0)
  93
  94         self.sync += self.meie.eq(0)
  95         self.sync += self.mtie.eq(0)
  96         self.sync += self.msie.eq(0)
  97
  98     def make(self):
  99         return Cat( self.usie, self.ssie, 0, self.msie,
 100                     self.utie, self.stie, 0, self.mtie,
 101                     self.ueie, self.seie, 0, self.meie, )
 102
 103
 104 class MIP:
 105     def __init__(self, comb, sync):
 106         self.comb = comb
 107         self.sync = sync
 108         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 109         self.seip = Signal(name="mip_seip")
 110         self.ueip = Signal(name="mip_uiep")
 111         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 112         self.stip = Signal(name="mip_stip")
 113         self.msip = Signal(name="mip_stip")
 114         self.utip = Signal(name="mip_utip")
 115         self.ssip = Signal(name="mip_ssip")
 116         self.usip = Signal(name="mip_usip")
 117
 118         for n in dir(self):
 119             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 120                 continue
 121             self.comb += getattr(self, n).eq(0x0)
 122
 123     def make(self):
 124         return Cat( self.usip, self.ssip, 0, self.msip,
 125                     self.utip, self.stip, 0, self.mtip,
 126                     self.ueip, self.seip, 0, self.meip, )
 127
 128
 129 class M:
 130     def __init__(self, comb, sync):
 131         self.comb = comb
 132         self.sync = sync
 133         self.mcause = Signal(32)
 134         self.mepc = Signal(32)
 135         self.mscratch = Signal(32)
 136         self.sync += self.mcause.eq(0)
 137         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 138         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 139
 140
 141 class Misa:
 142     def __init__(self, comb, sync):
 143         self.comb = comb
 144         self.sync = sync
 145         self.misa = Signal(32)
 146         cl = []
 147         for l in list(string.ascii_lowercase):
 148             value = 1 if l == 'i' else 0
 149             cl.append(Constant(value))
 150         cl.append(Constant(0, 4))
 151         cl.append(Constant(0b01, 2))
 152         self.comb += self.misa.eq(Cat(cl))
 153
 154
 155 class Fetch:
 156     def __init__(self, comb, sync):
 157         self.comb = comb
 158         self.sync = sync
 159         self.action = Signal(fetch_action, name="fetch_action")
 160         self.target_pc = Signal(32, name="fetch_target_pc")
 161         self.output_pc = Signal(32, name="fetch_output_pc")
 162         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 163         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 164
 165 class CSR:
 166     def __init__(self, comb, sync, dc, register_rs1):
 167         self.comb = comb
 168         self.sync = sync
 169         self.number = Signal(12, name="csr_number")
 170         self.input_value = Signal(32, name="csr_input_value")
 171         self.reads = Signal(name="csr_reads")
 172         self.writes = Signal(name="csr_writes")
 173         self.op_is_valid = Signal(name="csr_op_is_valid")
 174
 175         self.comb += self.number.eq(dc.immediate)
 176         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 177                                             dc.rs1,
 178                                             register_rs1))
 179         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 180         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 181
 182         self.comb += self.get_csr_op_is_valid()
 183
 184     def get_csr_op_is_valid(self):
 185         """ determines if a CSR is valid
 186         """
 187         c = {}
 188         # invalid csrs
 189         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 190                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 191                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 192                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 193                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 194                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 195                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 196             c[f] = self.op_is_valid.eq(0)
 197
 198         # not-writeable -> ok
 199         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 200                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 201                   csr_mimpid, csr_mhartid]:
 202             c[f] = self.op_is_valid.eq(~self.writes)
 203
 204         # valid csrs
 205         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 206                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 207             c[f] = self.op_is_valid.eq(1)
 208
 209         # not implemented / default
 210         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 211                   csr_mcycleh, csr_minstreth, "default"]:
 212             c[f] = self.op_is_valid.eq(0)
 213
 214         return Case(self.number, c)
 215
 216     def evaluate_csr_funct3_op(self, funct3, previous, written):
 217         c = { "default": written.eq(Constant(0, 32))}
 218         for f in [F3.csrrw, F3.csrrwi]:
 219             c[f] = written.eq(self.input_value)
 220         for f in [F3.csrrs, F3.csrrsi]:
 221             c[f] = written.eq(self.input_value | previous)
 222         for f in [F3.csrrc, F3.csrrci]:
 223             c[f] = written.eq(~self.input_value & previous)
 224         return Case(funct3, c)
 225
 226
 227 class MInfo:
 228     def __init__(self, comb):
 229         self.comb = comb
 230         # TODO
 231         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 232         self.time_counter    = Signal(64); # TODO: implement time_counter
 233         self.instret_counter = Signal(64); # TODO: implement instret_counter
 234
 235         self.mvendorid = Signal(32)
 236         self.marchid = Signal(32)
 237         self.mimpid = Signal(32)
 238         self.mhartid = Signal(32)
 239         self.comb += self.mvendorid.eq(Constant(0, 32))
 240         self.comb += self.marchid.eq(Constant(0, 32))
 241         self.comb += self.mimpid.eq(Constant(0, 32))
 242         self.comb += self.mhartid.eq(Constant(0, 32))
 243
 244 class Regs:
 245     def __init__(self, comb, sync):
 246         self.comb = comb
 247         self.sync = sync
 248
 249         self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en
 250         self.rs1 = Signal(32, name="regfile_rs1")
 251         self.rs_a = Signal(5, name="regfile_rs_a")
 252
 253         self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
 254         self.rs2 = Signal(32, name="regfile_rs2")
 255         self.rs_b = Signal(5, name="regfile_rs_b")
 256
 257         self.w_en = Signal(name="regfile_w_en")
 258         self.wval = Signal(32, name="regfile_wval")
 259         self.rd = Signal(32, name="regfile_rd")
 260
 261 class CPU(Module):
 262     """
 263     """
 264
 265     def get_lsbm(self, dc):
 266         return Cat(Constant(1),
 267                    Mux((dc.funct3[1] | dc.funct3[0]),
 268                        Constant(1), Constant(0)),
 269                    Mux((dc.funct3[1]),
 270                        Constant(0b11, 2), Constant(0, 2)))
 271
 272     # XXX this happens to get done by various self.sync actions
 273     #def reset_to_initial(self, m, mstatus, mie, registers):
 274     #    return [m.mcause.eq(0),
 275     #            ]
 276
 277     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 278         s = [ms.mpie.eq(ms.mie),
 279              ms.mie.eq(0),
 280              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 281                            ft.output_pc + 4,
 282                            ft.output_pc))]
 283
 284         # fetch action ack trap
 285         i = If(ft.action == FA.ack_trap,
 286                 m.mcause.eq(cause_instruction_access_fault)
 287               )
 288
 289         # ecall/ebreak
 290         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 291                 m.mcause.eq(Mux(dc.immediate[0],
 292                                 cause_machine_environment_call,
 293                                 cause_breakpoint))
 294               )
 295
 296         # load
 297         i = i.Elif((dc.act & DA.load) != 0,
 298                 If(load_store_misaligned,
 299                     m.mcause.eq(cause_load_address_misaligned)
 300                 ).Else(
 301                     m.mcause.eq(cause_load_access_fault)
 302                 )
 303               )
 304
 305         # store
 306         i = i.Elif((dc.act & DA.store) != 0,
 307                 If(load_store_misaligned,
 308                     m.mcause.eq(cause_store_amo_address_misaligned)
 309                 ).Else(
 310                     m.mcause.eq(cause_store_amo_access_fault)
 311                 )
 312               )
 313
 314         # jal/jalr -> misaligned=error, otherwise jump
 315         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 316                 m.mcause.eq(cause_instruction_address_misaligned)
 317               )
 318
 319         # defaults to illegal instruction
 320         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 321
 322         s.append(i)
 323         return s
 324
 325     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 326                          ft, dc,
 327                          load_store_misaligned,
 328                          loaded_value, alu_result,
 329                          lui_auipc_result):
 330         c = {}
 331         c[FOS.empty] = []
 332         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
 333                                        load_store_misaligned)
 334         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
 335                                        mstatus, mie, ft, dc,
 336                                        load_store_misaligned,
 337                                        loaded_value,
 338                                        alu_result,
 339                                        lui_auipc_result)
 340         return Case(ft.output_state, c)
 341
 342     def write_register(self, rd, val):
 343         return [self.regs.rd.eq(rd),
 344                 self.regs.wval.eq(val),
 345                 self.regs.w_en.eq(1)
 346                ]
 347
 348     def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 349                            ft, dc,
 350                            load_store_misaligned,
 351                            loaded_value, alu_result,
 352                            lui_auipc_result):
 353         # fetch action ack trap
 354         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 355                 [self.handle_trap(m, mstatus, ft, dc,
 356                                        load_store_misaligned),
 357                  self.regs.w_en.eq(0) # no writing to registers
 358                 ]
 359               )
 360
 361         # load
 362         i = i.Elif((dc.act & DA.load) != 0,
 363                 If(~mi.rw_wait,
 364                     self.write_register(dc.rd, loaded_value)
 365                 )
 366               )
 367
 368         # op or op_immediate
 369         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 370                 self.write_register(dc.rd, alu_result)
 371               )
 372
 373         # lui or auipc
 374         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 375                 self.write_register(dc.rd, lui_auipc_result)
 376               )
 377
 378         # jal/jalr
 379         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 380                 self.write_register(dc.rd, ft.output_pc + 4)
 381               )
 382
 383         i = i.Elif((dc.act & DA.csr) != 0,
 384                 self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
 385                                 dc, csr)
 386               )
 387
 388         # fence, store, branch
 389         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 390                               DA.store | DA.branch)) != 0,
 391                 # do nothing
 392                self.regs.w_en.eq(0) # no writing to registers
 393               )
 394
 395         return i
 396
 397     def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
 398         csr_output_value = Signal(32)
 399         csr_written_value = Signal(32)
 400         c = {}
 401
 402         # cycle
 403         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 404         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 405         # time
 406         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 407         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 408         # instret
 409         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 410         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 411         # mvendorid/march/mimpl/mhart
 412         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 413         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 414         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 415         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 416         # misa
 417         c[csr_misa     ] = csr_output_value.eq(misa.misa)
 418         # mstatus
 419         c[csr_mstatus  ] = [
 420             csr_output_value.eq(mstatus.mstatus),
 421             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 422                                                   csr_written_value),
 423             mstatus.mpie.eq(csr_written_value[7]),
 424             mstatus.mie.eq(csr_written_value[3])
 425         ]
 426         # mie
 427         c[csr_mie      ] = [
 428             csr_output_value.eq(mie.make()),
 429             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 430                                                   csr_written_value),
 431             mie.meie.eq(csr_written_value[11]),
 432             mie.mtie.eq(csr_written_value[7]),
 433             mie.msie.eq(csr_written_value[3]),
 434         ]
 435         # mtvec
 436         c[csr_mtvec    ] = csr_output_value.eq(mtvec)
 437         # mscratch
 438         c[csr_mscratch ] = [
 439             csr_output_value.eq(m.mscratch),
 440             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 441                                                   csr_written_value),
 442             If(csr.writes,
 443                 m.mscratch.eq(csr_written_value),
 444             )
 445         ]
 446         # mepc
 447         c[csr_mepc ] = [
 448             csr_output_value.eq(m.mepc),
 449             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 450                                                   csr_written_value),
 451             If(csr.writes,
 452                 m.mepc.eq(csr_written_value),
 453             )
 454         ]
 455
 456         # mcause
 457         c[csr_mcause ] = [
 458             csr_output_value.eq(m.mcause),
 459             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 460                                                   csr_written_value),
 461             If(csr.writes,
 462                 m.mcause.eq(csr_written_value),
 463             )
 464         ]
 465
 466         # mip
 467         c[csr_mip  ] = [
 468             csr_output_value.eq(mip.make()),
 469             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 470                                                   csr_written_value),
 471         ]
 472
 473         return [Case(csr.number, c),
 474                 If(csr.reads,
 475                     self.write_register(dc.rd, csr_output_value)
 476                 )]
 477
 478     def __init__(self):
 479         Module.__init__(self)
 480         self.clk = ClockSignal()
 481         self.reset = ResetSignal()
 482         self.tty_write = Signal()
 483         self.tty_write_data = Signal(8)
 484         self.tty_write_busy = Signal()
 485         self.switch_2 = Signal()
 486         self.switch_3 = Signal()
 487         self.led_1 = Signal()
 488         self.led_3 = Signal()
 489
 490         ram_size = Constant(0x8000)
 491         ram_start = Constant(0x10000, 32)
 492         reset_vector = Signal(32)
 493         mtvec = Signal(32)
 494
 495         reset_vector.eq(ram_start)
 496         mtvec.eq(ram_start + 0x40)
 497
 498         self.regs = Regs(self.comb, self.sync)
 499
 500         rf = Instance("RegFile", name="regfile",
 501            i_ra_en = self.regs.ra_en,
 502            i_rb_en = self.regs.rb_en,
 503            i_w_en = self.regs.w_en,
 504            o_read_a = self.regs.rs1,
 505            o_read_b = self.regs.rs2,
 506            i_writeval = self.regs.wval,
 507            i_rs_a = self.regs.rs_a,
 508            i_rs_b = self.regs.rs_b,
 509            i_rd = self.regs.rd)
 510
 511         self.specials += rf
 512
 513         mi = MemoryInterface()
 514
 515         mii = Instance("cpu_memory_interface", name="memory_instance",
 516                     p_ram_size = ram_size,
 517                     p_ram_start = ram_start,
 518                     i_clk=ClockSignal(),
 519                     i_rst=ResetSignal(),
 520                     i_fetch_address = mi.fetch_address,
 521                     o_fetch_data = mi.fetch_data,
 522                     o_fetch_valid = mi.fetch_valid,
 523                     i_rw_address = mi.rw_address,
 524                     i_rw_byte_mask = mi.rw_byte_mask,
 525                     i_rw_read_not_write = mi.rw_read_not_write,
 526                     i_rw_active = mi.rw_active,
 527                     i_rw_data_in = mi.rw_data_in,
 528                     o_rw_data_out = mi.rw_data_out,
 529                     o_rw_address_valid = mi.rw_address_valid,
 530                     o_rw_wait = mi.rw_wait,
 531                     o_tty_write = self.tty_write,
 532                     o_tty_write_data = self.tty_write_data,
 533                     i_tty_write_busy = self.tty_write_busy,
 534                     i_switch_2 = self.switch_2,
 535                     i_switch_3 = self.switch_3,
 536                     o_led_1 = self.led_1,
 537                     o_led_3 = self.led_3
 538                   )
 539         self.specials += mii
 540
 541         ft = Fetch(self.comb, self.sync)
 542
 543         fs = Instance("CPUFetchStage", name="fetch_stage",
 544             i_clk=ClockSignal(),
 545             i_rst=ResetSignal(),
 546             o_memory_interface_fetch_address = mi.fetch_address,
 547             i_memory_interface_fetch_data = mi.fetch_data,
 548             i_memory_interface_fetch_valid = mi.fetch_valid,
 549             i_fetch_action = ft.action,
 550             i_target_pc = ft.target_pc,
 551             o_output_pc = ft.output_pc,
 552             o_output_instruction = ft.output_instruction,
 553             o_output_state = ft.output_state,
 554             i_reset_vector = reset_vector,
 555             i_mtvec = mtvec,
 556         )
 557         self.specials += fs
 558
 559         dc = Decoder()
 560
 561         cd = Instance("CPUDecoder", name="decoder",
 562             i_instruction = ft.output_instruction,
 563             o_funct7 = dc.funct7,
 564             o_funct3 = dc.funct3,
 565             o_rd = dc.rd,
 566             o_rs1 = dc.rs1,
 567             o_rs2 = dc.rs2,
 568             o_immediate = dc.immediate,
 569             o_opcode = dc.opcode,
 570             o_decode_action = dc.act
 571         )
 572         self.specials += cd
 573
 574         self.comb += self.regs.rs_a.eq(dc.rs1)
 575         self.comb += self.regs.rs_b.eq(dc.rs2)
 576
 577         load_store_address = Signal(32)
 578         load_store_address_low_2 = Signal(2)
 579         load_store_misaligned = Signal()
 580         unmasked_loaded_value = Signal(32)
 581         loaded_value = Signal(32)
 582
 583         lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc",
 584             i_dc_immediate = dc.immediate,
 585             i_dc_funct3 = dc.funct3,
 586             i_rs1 = self.regs.rs1,
 587             i_rs2 = self.regs.rs2,
 588             i_rw_data_in = mi.rw_data_in,
 589             i_rw_data_out = mi.rw_data_out,
 590             o_load_store_address = load_store_address,
 591             o_load_store_address_low_2 = load_store_address_low_2,
 592             o_load_store_misaligned = load_store_misaligned,
 593             o_loaded_value = loaded_value)
 594
 595         self.specials += lsc
 596
 597         # XXX rwaddr not 31:2 any more
 598         self.comb += mi.rw_address.eq(load_store_address[2:])
 599
 600         unshifted_load_store_byte_mask = Signal(4)
 601
 602         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 603
 604         # XXX yuck.  this will cause migen simulation to fail
 605         # (however conversion to verilog works)
 606         self.comb += mi.rw_byte_mask.eq(
 607                 _Operator("<<", [unshifted_load_store_byte_mask,
 608                                         load_store_address_low_2]))
 609
 610         self.comb += mi.rw_active.eq(~self.reset
 611                         & (ft.output_state == FOS.valid)
 612                         & ~load_store_misaligned
 613                         & ((dc.act & (DA.load | DA.store)) != 0))
 614
 615         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 616
 617         # alu
 618         alu_a = Signal(32)
 619         alu_b = Signal(32)
 620         alu_result = Signal(32)
 621
 622         self.comb += alu_a.eq(self.regs.rs1)
 623         self.comb += alu_b.eq(Mux(dc.opcode[5],
 624                                   self.regs.rs2,
 625                                   dc.immediate))
 626
 627         ali = Instance("cpu_alu", name="alu",
 628             i_funct7 = dc.funct7,
 629             i_funct3 = dc.funct3,
 630             i_opcode = dc.opcode,
 631             i_a = alu_a,
 632             i_b = alu_b,
 633             o_result = alu_result
 634         )
 635         self.specials += ali
 636
 637         lui_auipc_result = Signal(32)
 638         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 639                                              dc.immediate,
 640                                              dc.immediate + ft.output_pc))
 641
 642         self.comb += ft.target_pc.eq(Cat(0,
 643                     Mux(dc.opcode != OP.jalr,
 644                                 ft.output_pc[1:32],
 645                                 self.regs.rs1[1:32] + dc.immediate[1:32])))
 646
 647         misaligned_jump_target = Signal()
 648         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 649
 650         branch_arg_a = Signal(32)
 651         branch_arg_b = Signal(32)
 652         self.comb += branch_arg_a.eq(Cat( self.regs.rs1[0:31],
 653                                           self.regs.rs1[31] ^ ~dc.funct3[1]))
 654         self.comb += branch_arg_b.eq(Cat( self.regs.rs2[0:31],
 655                                           self.regs.rs2[31] ^ ~dc.funct3[1]))
 656
 657         branch_taken = Signal()
 658         self.comb += branch_taken.eq(dc.funct3[0] ^
 659                                      Mux(dc.funct3[2],
 660                                          branch_arg_a < branch_arg_b,
 661                                          branch_arg_a == branch_arg_b))
 662
 663         m = M(self.comb, self.sync)
 664         mstatus = MStatus(self.comb, self.sync)
 665         mie = MIE(self.comb, self.sync)
 666         misa = Misa(self.comb, self.sync)
 667         mip = MIP(self.comb, self.sync)
 668
 669         ms = Instance("CPUMStatus", name="cpu_mstatus",
 670             o_mstatus = mstatus.mstatus,
 671             i_mpie = mstatus.mpie,
 672             i_mie = mstatus.mie)
 673
 674         self.specials += ms
 675
 676         # CSR decoding
 677         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
 678
 679         fi = Instance("CPUFetchAction", name="cpu_fetch_action",
 680             o_fetch_action = ft.action,
 681             i_output_state = ft.output_state,
 682             i_dc_act = dc.act,
 683             i_load_store_misaligned = load_store_misaligned,
 684             i_mi_rw_wait = mi.rw_wait,
 685             i_mi_rw_address_valid = mi.rw_address_valid,
 686             i_branch_taken = branch_taken,
 687             i_misaligned_jump_target = misaligned_jump_target,
 688             i_csr_op_is_valid = csr.op_is_valid)
 689
 690         self.specials += fi
 691
 692         minfo = MInfo(self.comb)
 693
 694         self.sync += If(~self.reset,
 695                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
 696                                         mstatus, mie, ft, dc,
 697                                         load_store_misaligned,
 698                                         loaded_value,
 699                                        alu_result,
 700                                        lui_auipc_result)
 701                      )
 702
 703 if __name__ == "__main__":
 704     example = CPU()
 705     print(verilog.convert(example,
 706          {
 707            example.tty_write,
 708            example.tty_write_data,
 709            example.tty_write_busy,
 710            example.switch_2,
 711            example.switch_3,
 712            example.led_1,
 713            example.led_3,
 714            }))