cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.ueie = Signal(name="mie_ueie")
 111         self.stie = Signal(name="mie_stie")
 112         self.utie = Signal(name="mie_utie")
 113         self.ssie = Signal(name="mie_ssie")
 114         self.usie = Signal(name="mie_usie")
 115
 116         for n in dir(self):
 117             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 118                 continue
 119             self.comb += getattr(self, n).eq(0x0)
 120
 121         self.sync += self.meie.eq(0)
 122         self.sync += self.mtie.eq(0)
 123         self.sync += self.msie.eq(0)
 124
 125 class MIP:
 126     def __init__(self, comb, sync):
 127         self.comb = comb
 128         self.sync = sync
 129         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 130         self.seip = Signal(name="mip_seip")
 131         self.ueip = Signal(name="mip_uiep")
 132         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 133         self.stip = Signal(name="mip_stip")
 134         self.msip = Signal(name="mip_stip")
 135         self.utip = Signal(name="mip_utip")
 136         self.ssip = Signal(name="mip_ssip")
 137         self.usip = Signal(name="mip_usip")
 138
 139         for n in dir(self):
 140             if n in ['comb', 'sync'] or n.startswith("_"):
 141                 continue
 142             self.comb += getattr(self, n).eq(0x0)
 143
 144
 145 class M:
 146     def __init__(self, comb, sync):
 147         self.comb = comb
 148         self.sync = sync
 149         self.mcause = Signal(32)
 150         self.mepc = Signal(32)
 151         self.mscratch = Signal(32)
 152         self.sync += self.mcause.eq(0)
 153         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 154         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 155
 156
 157 class Misa:
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.misa = Signal(32)
 162         cl = []
 163         for l in list(string.ascii_lowercase):
 164             value = 1 if l == 'i' else 0
 165             cl.append(Constant(value))
 166         cl.append(Constant(0, 4))
 167         cl.append(Constant(0b01, 2))
 168         self.comb += self.misa.eq(Cat(cl))
 169
 170
 171 class Fetch:
 172     def __init__(self, comb, sync):
 173         self.comb = comb
 174         self.sync = sync
 175         self.action = Signal(fetch_action, name="fetch_action")
 176         self.target_pc = Signal(32, name="fetch_target_pc")
 177         self.output_pc = Signal(32, name="fetch_output_pc")
 178         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 179         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 180
 181     def get_fetch_action(self, dc, load_store_misaligned, mi,
 182                          branch_taken, misaligned_jump_target,
 183                          csr_op_is_valid):
 184         c = {}
 185         c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
 186         c[FOS.empty] = self.action.eq(FA.default)
 187         c[FOS.trap] = self.action.eq(FA.ack_trap)
 188
 189         # illegal instruction -> error trap
 190         i= If((dc.act & DA.trap_illegal_instruction) != 0,
 191                  self.action.eq(FA.error_trap)
 192               )
 193
 194         # ecall / ebreak -> noerror trap
 195         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 196                  self.action.eq(FA.noerror_trap))
 197
 198         # load/store: check alignment, check wait
 199         i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
 200                 If((load_store_misaligned | ~mi.rw_address_valid),
 201                     self.action.eq(FA.error_trap) # misaligned or invalid addr
 202                 ).Elif(mi.rw_wait,
 203                     self.action.eq(FA.wait) # wait
 204                 ).Else(
 205                     self.action.eq(FA.default) # ok
 206                 )
 207               )
 208
 209         # fence
 210         i = i.Elif((dc.act & DA.fence) != 0,
 211                  self.action.eq(FA.fence))
 212
 213         # branch -> misaligned=error, otherwise jump
 214         i = i.Elif((dc.act & DA.branch) != 0,
 215                 If(misaligned_jump_target,
 216                     self.action.eq(FA.error_trap)
 217                 ).Else(
 218                     self.action.eq(FA.jump)
 219                 )
 220               )
 221
 222         # jal/jalr -> misaligned=error, otherwise jump
 223         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 224                 If(misaligned_jump_target,
 225                     self.action.eq(FA.error_trap)
 226                 ).Else(
 227                     self.action.eq(FA.jump)
 228                 )
 229               )
 230
 231         # csr -> opvalid=ok, else error trap
 232         i = i.Elif((dc.act & DA.csr) != 0,
 233                 If(csr_op_is_valid,
 234                     self.action.eq(FA.default)
 235                 ).Else(
 236                     self.action.eq(FA.error_trap)
 237                 )
 238               )
 239
 240         c[FOS.valid] = i
 241
 242         return Case(self.output_state, c)
 243
 244
 245 class CPU(Module):
 246     """
 247     """
 248
 249     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 250         """ returns whether a load/store is misaligned
 251         """
 252         return Case(funct3[:2],
 253                 { F3.sb: ls.eq(Constant(0)),
 254                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 255                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 256                   "default": ls.eq(Constant(1))
 257                 })
 258
 259     def get_lsbm(self, dc):
 260         return Cat(Constant(1),
 261                    Mux((dc.funct3[1] | dc.funct3[0]),
 262                        Constant(1), Constant(0)),
 263                    Mux((dc.funct3[1]),
 264                        Constant(0b11, 2), Constant(0, 2)))
 265
 266     # XXX this happens to get done by various self.sync actions
 267     #def reset_to_initial(self, m, mstatus, mie, registers):
 268     #    return [m.mcause.eq(0),
 269     #            ]
 270
 271     def write_register(self, register_number, value):
 272         return If(register_number != 0,
 273                   self.registers[register_number].eq(value)
 274                )
 275
 276     def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
 277         c = { "default": Constant(0, 32)}
 278         for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
 279         for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
 280         for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
 281         return Case(funct3, c)
 282
 283     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 284         s = [ms.mpie.eq(ms.mie),
 285              ms.mie.eq(0),
 286              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 287                            ft.output_pc + 4,
 288                            ft.output_pc))]
 289
 290         # fetch action ack trap
 291         i = If(ft.action == FA.ack_trap,
 292                 m.mcause.eq(cause_instruction_access_fault)
 293               )
 294
 295         # ecall/ebreak
 296         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 297                 m.mcause.eq(Mux(dc.immediate[0],
 298                                 cause_machine_environment_call,
 299                                 cause_breakpoint))
 300               )
 301
 302         # load
 303         i = i.Elif((dc.act & DA.load) != 0,
 304                 If(load_store_misaligned,
 305                     m.mcause.eq(cause_load_address_misaligned)
 306                 ).Else(
 307                     m.mcause.eq(cause_load_access_fault)
 308                 )
 309               )
 310
 311         # store
 312         i = i.Elif((dc.act & DA.store) != 0,
 313                 If(load_store_misaligned,
 314                     m.mcause.eq(cause_store_amo_address_misaligned)
 315                 ).Else(
 316                     m.mcause.eq(cause_store_amo_access_fault)
 317                 )
 318               )
 319
 320         # jal/jalr -> misaligned=error, otherwise jump
 321         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 322                 m.mcause.eq(cause_instruction_address_misaligned)
 323               )
 324
 325         # defaults to illegal instruction
 326         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 327
 328         s.append(i)
 329         return s
 330
 331     """
 332     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 333     begin
 334         case(csr_number)
 335         `csr_ustatus,
 336         `csr_fflags,
 337         `csr_frm,
 338         `csr_fcsr,
 339         `csr_uie,
 340         `csr_utvec,
 341         `csr_uscratch,
 342         `csr_uepc,
 343         `csr_ucause,
 344         `csr_utval,
 345         `csr_uip,
 346         `csr_sstatus,
 347         `csr_sedeleg,
 348         `csr_sideleg,
 349         `csr_sie,
 350         `csr_stvec,
 351         `csr_scounteren,
 352         `csr_sscratch,
 353         `csr_sepc,
 354         `csr_scause,
 355         `csr_stval,
 356         `csr_sip,
 357         `csr_satp,
 358         `csr_medeleg,
 359         `csr_mideleg,
 360         `csr_dcsr,
 361         `csr_dpc,
 362         `csr_dscratch:
 363             get_csr_op_is_valid = 0;
 364         `csr_cycle,
 365         `csr_time,
 366         `csr_instret,
 367         `csr_cycleh,
 368         `csr_timeh,
 369         `csr_instreth,
 370         `csr_mvendorid,
 371         `csr_marchid,
 372         `csr_mimpid,
 373         `csr_mhartid:
 374             get_csr_op_is_valid = ~csr_writes;
 375         `csr_misa,
 376         `csr_mstatus,
 377         `csr_mie,
 378         `csr_mtvec,
 379         `csr_mscratch,
 380         `csr_mepc,
 381         `csr_mcause,
 382         `csr_mip:
 383             get_csr_op_is_valid = 1;
 384         `csr_mcounteren,
 385         `csr_mtval,
 386         `csr_mcycle,
 387         `csr_minstret,
 388         `csr_mcycleh,
 389         `csr_minstreth:
 390             // TODO: CSRs not implemented yet
 391             get_csr_op_is_valid = 0;
 392         endcase
 393     end
 394     endfunction
 395
 396     """
 397
 398     def __init__(self):
 399         self.clk = ClockSignal()
 400         self.reset = ResetSignal()
 401         self.tty_write = Signal()
 402         self.tty_write_data = Signal(8)
 403         self.tty_write_busy = Signal()
 404         self.switch_2 = Signal()
 405         self.switch_3 = Signal()
 406         self.led_1 = Signal()
 407         self.led_3 = Signal()
 408
 409         ram_size = Constant(0x8000)
 410         ram_start = Constant(0x10000, 32)
 411         reset_vector = Signal(32)
 412         mtvec = Signal(32)
 413
 414         reset_vector.eq(ram_start)
 415         mtvec.eq(ram_start + 0x40)
 416
 417         l = []
 418         for i in range(31):
 419             r = Signal(32, name="register%d" % i)
 420             l.append(r)
 421             self.sync += r.eq(Constant(0, 32))
 422         self.registers = Array(l)
 423
 424         mi = MemoryInterface()
 425
 426         mii = Instance("cpu_memory_interface", name="memory_instance",
 427                     p_ram_size = ram_size,
 428                     p_ram_start = ram_start,
 429                     i_clk=ClockSignal(),
 430                     i_rst=ResetSignal(),
 431                     i_fetch_address = mi.fetch_address,
 432                     o_fetch_data = mi.fetch_data,
 433                     o_fetch_valid = mi.fetch_valid,
 434                     i_rw_address = mi.rw_address,
 435                     i_rw_byte_mask = mi.rw_byte_mask,
 436                     i_rw_read_not_write = mi.rw_read_not_write,
 437                     i_rw_active = mi.rw_active,
 438                     i_rw_data_in = mi.rw_data_in,
 439                     o_rw_data_out = mi.rw_data_out,
 440                     o_rw_address_valid = mi.rw_address_valid,
 441                     o_rw_wait = mi.rw_wait,
 442                     o_tty_write = self.tty_write,
 443                     o_tty_write_data = self.tty_write_data,
 444                     i_tty_write_busy = self.tty_write_busy,
 445                     i_switch_2 = self.switch_2,
 446                     i_switch_3 = self.switch_3,
 447                     o_led_1 = self.led_1,
 448                     o_led_3 = self.led_3
 449                   )
 450         self.specials += mii
 451
 452         ft = Fetch(self.comb, self.sync)
 453
 454         fs = Instance("CPUFetchStage", name="fetch_stage",
 455             i_clk=ClockSignal(),
 456             i_rst=ResetSignal(),
 457             o_memory_interface_fetch_address = mi.fetch_address,
 458             i_memory_interface_fetch_data = mi.fetch_data,
 459             i_memory_interface_fetch_valid = mi.fetch_valid,
 460             i_fetch_action = ft.action,
 461             i_target_pc = ft.target_pc,
 462             o_output_pc = ft.output_pc,
 463             o_output_instruction = ft.output_instruction,
 464             o_output_state = ft.output_state,
 465             i_reset_vector = reset_vector,
 466             i_mtvec = mtvec,
 467         )
 468         self.specials += fs
 469
 470         dc = Decoder()
 471
 472         cd = Instance("CPUDecoder", name="decoder",
 473             i_instruction = ft.output_instruction,
 474             o_funct7 = dc.funct7,
 475             o_funct3 = dc.funct3,
 476             o_rd = dc.rd,
 477             o_rs1 = dc.rs1,
 478             o_rs2 = dc.rs2,
 479             o_immediate = dc.immediate,
 480             o_opcode = dc.opcode,
 481             o_decode_action = dc.act
 482         )
 483         self.specials += cd
 484
 485         register_rs1 = Signal(32)
 486         register_rs2 = Signal(32)
 487         self.comb += If(dc.rs1 == 0,
 488                         register_rs1.eq(0)
 489                      ).Else(
 490                         register_rs1.eq(self.registers[dc.rs1-1]))
 491         self.comb += If(dc.rs2 == 0,
 492                         register_rs2.eq(0)
 493                      ).Else(
 494                         register_rs2.eq(self.registers[dc.rs2-1]))
 495
 496         load_store_address = Signal(32)
 497         load_store_address_low_2 = Signal(2)
 498
 499         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 500         self.comb += load_store_address_low_2.eq(
 501                             dc.immediate[:2] + register_rs1[:2])
 502
 503         load_store_misaligned = Signal()
 504
 505         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 506                                      load_store_address_low_2)
 507         self.comb += lsa
 508
 509         # XXX rwaddr not 31:2 any more
 510         self.comb += mi.rw_address.eq(load_store_address[2:])
 511
 512         unshifted_load_store_byte_mask = Signal(4)
 513
 514         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 515
 516         # XXX yuck.  this will cause migen simulation to fail
 517         # (however conversion to verilog works)
 518         self.comb += mi.rw_byte_mask.eq(
 519                 _Operator("<<", [unshifted_load_store_byte_mask,
 520                                         load_store_address_low_2]))
 521
 522         # XXX not obvious
 523         b3 = Mux(load_store_address_low_2[1],
 524                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 525                                                   register_rs2[8:16]),
 526                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 527                                                   register_rs2[24:32]))
 528         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 529                                               register_rs2[16:24])
 530         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 531                                               register_rs2[8:16])
 532         b0 = register_rs2[0:8]
 533
 534         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 535
 536         # XXX not obvious
 537         unmasked_loaded_value = Signal(32)
 538
 539         b0 = Mux(load_store_address_low_2[1],
 540                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 541                                                   mi.rw_data_out[16:24]),
 542                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 543                                                   mi.rw_data_out[0:8]))
 544         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 545                                               mi.rw_data_out[8:16])
 546         b23 = mi.rw_data_out[16:32]
 547
 548         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 549
 550         # XXX not obvious
 551         loaded_value = Signal(32)
 552
 553         b0 = unmasked_loaded_value[0:8]
 554         b1 = Mux(dc.funct3[0:2] == 0,
 555                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 556                 unmasked_loaded_value[8:16])
 557         b2 = Mux(dc.funct3[1] == 0,
 558                 Replicate(~dc.funct3[2] &
 559                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 560                                                   unmasked_loaded_value[7]),
 561                           16),
 562                 unmasked_loaded_value[16:32])
 563
 564         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 565
 566         self.comb += mi.rw_active.eq(~self.reset
 567                         & (ft.output_state == FOS.valid)
 568                         & ~load_store_misaligned
 569                         & ((dc.act & (DA.load | DA.store)) != 0))
 570
 571         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 572
 573         # alu
 574         alu_a = Signal(32)
 575         alu_b = Signal(32)
 576         alu_result = Signal(32)
 577
 578         self.comb += alu_a.eq(register_rs1)
 579         self.comb += alu_b.eq(Mux(dc.opcode[5],
 580                                   register_rs2,
 581                                   dc.immediate))
 582
 583         ali = Instance("cpu_alu", name="alu",
 584             i_funct7 = dc.funct7,
 585             i_funct3 = dc.funct3,
 586             i_opcode = dc.opcode,
 587             i_a = alu_a,
 588             i_b = alu_b,
 589             o_result = alu_result
 590         )
 591         self.specials += ali
 592
 593         lui_auipc_result = Signal(32)
 594         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 595                                              dc.immediate,
 596                                              dc.immediate + ft.output_pc))
 597
 598         self.comb += ft.target_pc.eq(Cat(0,
 599                     Mux(dc.opcode != OP.jalr,
 600                                 ft.output_pc[1:32],
 601                                 register_rs1[1:32] + dc.immediate[1:32])))
 602
 603         misaligned_jump_target = Signal()
 604         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 605
 606         branch_arg_a = Signal(32)
 607         branch_arg_b = Signal(32)
 608         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 609                                           register_rs1[31] ^ ~dc.funct3[1]))
 610         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 611                                           register_rs2[31] ^ ~dc.funct3[1]))
 612
 613         branch_taken = Signal()
 614         self.comb += branch_taken.eq(dc.funct3[0] ^
 615                                      Mux(dc.funct3[2],
 616                                          branch_arg_a < branch_arg_b,
 617                                          branch_arg_a == branch_arg_b))
 618
 619         m = M(self.comb, self.sync)
 620         mstatus = MStatus(self.comb, self.sync)
 621         mie = MIE(self.comb, self.sync)
 622
 623         misa = Misa(self.comb, self.sync)
 624
 625         mvendorid = Signal(32)
 626         marchid = Signal(32)
 627         mimpid = Signal(32)
 628         mhartid = Signal(32)
 629         self.comb += mvendorid.eq(Constant(0, 32))
 630         self.comb += marchid.eq(Constant(0, 32))
 631         self.comb += mimpid.eq(Constant(0, 32))
 632         self.comb += mhartid.eq(Constant(0, 32))
 633
 634         mip = MIP(self.comb, self.sync)
 635
 636         csr_op_is_valid = Signal()
 637
 638         self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
 639                                  branch_taken, misaligned_jump_target,
 640                                  csr_op_is_valid)
 641
 642         #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
 643         # CSR decoding
 644         csr_number = Signal(12)
 645         csr_input_value = Signal(32)
 646         csr_reads = Signal()
 647         csr_writes = Signal()
 648
 649         self.comb += csr_number.eq(dc.immediate)
 650         self.comb += csr_input_value.eq(Mux(dc.funct3[2],
 651                                             dc.rs1,
 652                                             register_rs1))
 653         self.comb += csr_reads.eq(dc.funct3[1] | (dc.rd != 0))
 654         self.comb += csr_writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 655
 656
 657 if __name__ == "__main__":
 658     example = CPU()
 659     print(verilog.convert(example,
 660          {
 661            example.tty_write,
 662            example.tty_write_data,
 663            example.tty_write_busy,
 664            example.switch_2,
 665            example.switch_3,
 666            example.led_1,
 667            example.led_3,
 668            }))
 669
 670 """
 671
 672     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 673     begin
 674         case(csr_number)
 675         `csr_ustatus,
 676         `csr_fflags,
 677         `csr_frm,
 678         `csr_fcsr,
 679         `csr_uie,
 680         `csr_utvec,
 681         `csr_uscratch,
 682         `csr_uepc,
 683         `csr_ucause,
 684         `csr_utval,
 685         `csr_uip,
 686         `csr_sstatus,
 687         `csr_sedeleg,
 688         `csr_sideleg,
 689         `csr_sie,
 690         `csr_stvec,
 691         `csr_scounteren,
 692         `csr_sscratch,
 693         `csr_sepc,
 694         `csr_scause,
 695         `csr_stval,
 696         `csr_sip,
 697         `csr_satp,
 698         `csr_medeleg,
 699         `csr_mideleg,
 700         `csr_dcsr,
 701         `csr_dpc,
 702         `csr_dscratch:
 703             get_csr_op_is_valid = 0;
 704         `csr_cycle,
 705         `csr_time,
 706         `csr_instret,
 707         `csr_cycleh,
 708         `csr_timeh,
 709         `csr_instreth,
 710         `csr_mvendorid,
 711         `csr_marchid,
 712         `csr_mimpid,
 713         `csr_mhartid:
 714             get_csr_op_is_valid = ~csr_writes;
 715         `csr_misa,
 716         `csr_mstatus,
 717         `csr_mie,
 718         `csr_mtvec,
 719         `csr_mscratch,
 720         `csr_mepc,
 721         `csr_mcause,
 722         `csr_mip:
 723             get_csr_op_is_valid = 1;
 724         `csr_mcounteren,
 725         `csr_mtval,
 726         `csr_mcycle,
 727         `csr_minstret,
 728         `csr_mcycleh,
 729         `csr_minstreth:
 730             // TODO: CSRs not implemented yet
 731             get_csr_op_is_valid = 0;
 732         endcase
 733     end
 734     endfunction
 735
 736     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 737
 738     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 739     wire [63:0] time_counter = 0; // TODO: implement time_counter
 740     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 741
 742     always @(posedge clk) begin:main_block
 743         if(reset) begin
 744             reset_to_initial();
 745             disable main_block;
 746         end
 747         case(fetch_output_state)
 748         `fetch_output_state_empty: begin
 749         end
 750         `fetch_output_state_trap: begin
 751             handle_trap();
 752         end
 753         `fetch_output_state_valid: begin:valid
 754             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 755                 handle_trap();
 756             end
 757             else if((decode_action & `decode_action_load) != 0) begin
 758                 if(~memory_interface_rw_wait)
 759                     write_register(decoder_rd, loaded_value);
 760             end
 761             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 762                 write_register(decoder_rd, alu_result);
 763             end
 764             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 765                 write_register(decoder_rd, lui_auipc_result);
 766             end
 767             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 768                 write_register(decoder_rd, fetch_output_pc + 4);
 769             end
 770             else if((decode_action & `decode_action_csr) != 0) begin:csr
 771                 reg [31:0] csr_output_value;
 772                 reg [31:0] csr_written_value;
 773                 csr_output_value = 32'hXXXXXXXX;
 774                 csr_written_value = 32'hXXXXXXXX;
 775                 case(csr_number)
 776                 `csr_cycle: begin
 777                     csr_output_value = cycle_counter[31:0];
 778                 end
 779                 `csr_time: begin
 780                     csr_output_value = time_counter[31:0];
 781                 end
 782                 `csr_instret: begin
 783                     csr_output_value = instret_counter[31:0];
 784                 end
 785                 `csr_cycleh: begin
 786                     csr_output_value = cycle_counter[63:32];
 787                 end
 788                 `csr_timeh: begin
 789                     csr_output_value = time_counter[63:32];
 790                 end
 791                 `csr_instreth: begin
 792                     csr_output_value = instret_counter[63:32];
 793                 end
 794                 `csr_mvendorid: begin
 795                     csr_output_value = mvendorid;
 796                 end
 797                 `csr_marchid: begin
 798                     csr_output_value = marchid;
 799                 end
 800                 `csr_mimpid: begin
 801                     csr_output_value = mimpid;
 802                 end
 803                 `csr_mhartid: begin
 804                     csr_output_value = mhartid;
 805                 end
 806                 `csr_misa: begin
 807                     csr_output_value = misa;
 808                 end
 809                 `csr_mstatus: begin
 810                     csr_output_value = make_mstatus(mstatus_tsr,
 811                                                     mstatus_tw,
 812                                                     mstatus_tvm,
 813                                                     mstatus_mxr,
 814                                                     mstatus_sum,
 815                                                     mstatus_mprv,
 816                                                     mstatus_xs,
 817                                                     mstatus_fs,
 818                                                     mstatus_mpp,
 819                                                     mstatus_spp,
 820                                                     mstatus_mpie,
 821                                                     mstatus_spie,
 822                                                     mstatus_upie,
 823                                                     mstatus_mie,
 824                                                     mstatus_sie,
 825                                                     mstatus_uie);
 826                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 827                     if(csr_writes) begin
 828                         mstatus_mpie = csr_written_value[7];
 829                         mstatus_mie = csr_written_value[3];
 830                     end
 831                 end
 832                 `csr_mie: begin
 833                     csr_output_value = 0;
 834                     csr_output_value[11] = mie_meie;
 835                     csr_output_value[9] = mie_seie;
 836                     csr_output_value[8] = mie_ueie;
 837                     csr_output_value[7] = mie_mtie;
 838                     csr_output_value[5] = mie_stie;
 839                     csr_output_value[4] = mie_utie;
 840                     csr_output_value[3] = mie_msie;
 841                     csr_output_value[1] = mie_ssie;
 842                     csr_output_value[0] = mie_usie;
 843                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 844                     if(csr_writes) begin
 845                         mie_meie = csr_written_value[11];
 846                         mie_mtie = csr_written_value[7];
 847                         mie_msie = csr_written_value[3];
 848                     end
 849                 end
 850                 `csr_mtvec: begin
 851                     csr_output_value = mtvec;
 852                 end
 853                 `csr_mscratch: begin
 854                     csr_output_value = mscratch;
 855                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 856                     if(csr_writes)
 857                         mscratch = csr_written_value;
 858                 end
 859                 `csr_mepc: begin
 860                     csr_output_value = mepc;
 861                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 862                     if(csr_writes)
 863                         mepc = csr_written_value;
 864                 end
 865                 `csr_mcause: begin
 866                     csr_output_value = mcause;
 867                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 868                     if(csr_writes)
 869                         mcause = csr_written_value;
 870                 end
 871                 `csr_mip: begin
 872                     csr_output_value = 0;
 873                     csr_output_value[11] = mip_meip;
 874                     csr_output_value[9] = mip_seip;
 875                     csr_output_value[8] = mip_ueip;
 876                     csr_output_value[7] = mip_mtip;
 877                     csr_output_value[5] = mip_stip;
 878                     csr_output_value[4] = mip_utip;
 879                     csr_output_value[3] = mip_msip;
 880                     csr_output_value[1] = mip_ssip;
 881                     csr_output_value[0] = mip_usip;
 882                 end
 883                 endcase
 884                 if(csr_reads)
 885                     write_register(decoder_rd, csr_output_value);
 886             end
 887             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 888                 // do nothing
 889             end
 890         end
 891         endcase
 892     end
 893
 894 endmodule
 895 """
 896