cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31
  32 from riscvdefs import *
  33 from cpudefs import *
  34
  35 class CPU(Module):
  36     """
  37     """
  38
  39     def __init__(self):
  40         #self.clk = ClockSignal()
  41         #self.reset = ResetSignal()
  42         self.tty_write = Signal()
  43         self.tty_write_data = Signal(8)
  44         self.tty_write_busy = Signal()
  45         self.switch_2 = Signal()
  46         self.switch_3 = Signal()
  47         self.led_1 = Signal()
  48         self.led_3 = Signal()
  49
  50         ram_size = Constant(0x8000)
  51         ram_start = Constant(0x10000, 32)
  52         reset_vector = Signal(32)
  53         mtvec = Signal(32)
  54
  55         reset_vector.eq(ram_start)
  56         mtvec.eq(ram_start + 0x40)
  57
  58         l = []
  59         for i in range(31):
  60             l.append(Signal(32, name="register%d" % i))
  61         self.registers = Array(l)
  62
  63         #self.sync += self.registers[0].eq(0)
  64         #self.sync += self.registers[1].eq(0)
  65
  66         memory_interface_fetch_address = Signal(32)[2:]
  67         memory_interface_fetch_data = Signal(32)
  68         memory_interface_fetch_valid = Signal()
  69         memory_interface_rw_address= Signal(32)[2:]
  70         memory_interface_rw_byte_mask = Signal(4)
  71         memory_interface_rw_read_not_write = Signal()
  72         memory_interface_rw_active = Signal()
  73         memory_interface_rw_data_in = Signal(32)
  74         memory_interface_rw_data_out = Signal(32)
  75         memory_interface_rw_address_valid = Signal()
  76         memory_interface_rw_wait = Signal()
  77
  78         mi = Instance("cpu_memory_interface",
  79                     p_ram_size = ram_size,
  80                     p_ram_start = ram_start,
  81                     i_clk=ClockSignal(),
  82                     i_rst=ResetSignal(),
  83                     i_fetch_address = memory_interface_fetch_address,
  84                     o_fetch_data = memory_interface_fetch_data,
  85                     o_fetch_valid = memory_interface_fetch_valid,
  86                     i_rw_address = memory_interface_rw_address,
  87                     i_rw_byte_mask = memory_interface_rw_byte_mask,
  88                     i_rw_read_not_write = memory_interface_rw_read_not_write,
  89                     i_rw_active = memory_interface_rw_active,
  90                     i_rw_data_in = memory_interface_rw_data_in,
  91                     o_rw_data_out = memory_interface_rw_data_out,
  92                     o_rw_address_valid = memory_interface_rw_address_valid,
  93                     o_rw_wait = memory_interface_rw_wait,
  94                     o_tty_write = self.tty_write,
  95                     o_tty_write_data = self.tty_write_data,
  96                     i_tty_write_busy = self.tty_write_busy,
  97                     i_switch_2 = self.switch_2,
  98                     i_switch_3 = self.switch_3,
  99                     o_led_1 = self.led_1,
 100                     o_led_3 = self.led_3
 101                   )
 102         self.specials += mi
 103
 104 """
 105     cpu_memory_interface #(
 106         .ram_size(ram_size),
 107         .ram_start(ram_start)
 108         ) memory_interface(
 109         .clk(clk),
 110         .reset(reset),
 111         .fetch_address(memory_interface_fetch_address),
 112         .fetch_data(memory_interface_fetch_data),
 113         .fetch_valid(memory_interface_fetch_valid),
 114         .rw_address(memory_interface_rw_address),
 115         .rw_byte_mask(memory_interface_rw_byte_mask),
 116         .rw_read_not_write(memory_interface_rw_read_not_write),
 117         .rw_active(memory_interface_rw_active),
 118         .rw_data_in(memory_interface_rw_data_in),
 119         .rw_data_out(memory_interface_rw_data_out),
 120         .rw_address_valid(memory_interface_rw_address_valid),
 121         .rw_wait(memory_interface_rw_wait),
 122         .tty_write(tty_write),
 123         .tty_write_data(tty_write_data),
 124         .tty_write_busy(tty_write_busy),
 125         .switch_2(switch_2),
 126         .switch_3(switch_3),
 127         .led_1(led_1),
 128         .led_3(led_3)
 129         );
 130 """
 131
 132 if __name__ == "__main__":
 133     example = CPU()
 134     print(verilog.convert(example,
 135          {
 136            example.tty_write,
 137            example.tty_write_data,
 138            example.tty_write_busy,
 139            example.switch_2,
 140            example.switch_3,
 141            example.led_1,
 142            example.led_3,
 143            }))
 144
 145 """
 146 module cpu(
 147     input clk,
 148     input reset,
 149     output tty_write,
 150     output [7:0] tty_write_data,
 151     input tty_write_busy,
 152     input switch_2,
 153     input switch_3,
 154     output led_1,
 155     output led_3
 156     );
 157
 158     parameter ram_size = 'h8000;
 159     parameter ram_start = 32'h1_0000;
 160     parameter reset_vector = ram_start;
 161     parameter mtvec = ram_start + 'h40;
 162
 163     reg [31:0] registers[31:1];
 164
 165     wire [31:2] memory_interface_fetch_address;
 166     wire [31:0] memory_interface_fetch_data;
 167     wire memory_interface_fetch_valid;
 168     wire [31:2] memory_interface_rw_address;
 169     wire [3:0] memory_interface_rw_byte_mask;
 170     wire memory_interface_rw_read_not_write;
 171     wire memory_interface_rw_active;
 172     wire [31:0] memory_interface_rw_data_in;
 173     wire [31:0] memory_interface_rw_data_out;
 174     wire memory_interface_rw_address_valid;
 175     wire memory_interface_rw_wait;
 176
 177     cpu_memory_interface #(
 178         .ram_size(ram_size),
 179         .ram_start(ram_start)
 180         ) memory_interface(
 181         .clk(clk),
 182         .reset(reset),
 183         .fetch_address(memory_interface_fetch_address),
 184         .fetch_data(memory_interface_fetch_data),
 185         .fetch_valid(memory_interface_fetch_valid),
 186         .rw_address(memory_interface_rw_address),
 187         .rw_byte_mask(memory_interface_rw_byte_mask),
 188         .rw_read_not_write(memory_interface_rw_read_not_write),
 189         .rw_active(memory_interface_rw_active),
 190         .rw_data_in(memory_interface_rw_data_in),
 191         .rw_data_out(memory_interface_rw_data_out),
 192         .rw_address_valid(memory_interface_rw_address_valid),
 193         .rw_wait(memory_interface_rw_wait),
 194         .tty_write(tty_write),
 195         .tty_write_data(tty_write_data),
 196         .tty_write_busy(tty_write_busy),
 197         .switch_2(switch_2),
 198         .switch_3(switch_3),
 199         .led_1(led_1),
 200         .led_3(led_3)
 201         );
 202
 203     wire `fetch_action fetch_action;
 204     wire [31:0] fetch_target_pc;
 205     wire [31:0] fetch_output_pc;
 206     wire [31:0] fetch_output_instruction;
 207     wire `fetch_output_state fetch_output_state;
 208
 209     cpu_fetch_stage #(
 210         .reset_vector(reset_vector),
 211         .mtvec(mtvec)
 212         ) fetch_stage(
 213         .clk(clk),
 214         .reset(reset),
 215         .memory_interface_fetch_address(memory_interface_fetch_address),
 216         .memory_interface_fetch_data(memory_interface_fetch_data),
 217         .memory_interface_fetch_valid(memory_interface_fetch_valid),
 218         .fetch_action(fetch_action),
 219         .target_pc(fetch_target_pc),
 220         .output_pc(fetch_output_pc),
 221         .output_instruction(fetch_output_instruction),
 222         .output_state(fetch_output_state)
 223         );
 224
 225     wire [6:0] decoder_funct7;
 226     wire [2:0] decoder_funct3;
 227     wire [4:0] decoder_rd;
 228     wire [4:0] decoder_rs1;
 229     wire [4:0] decoder_rs2;
 230     wire [31:0] decoder_immediate;
 231     wire [6:0] decoder_opcode;
 232     wire `decode_action decode_action;
 233
 234     cpu_decoder decoder(
 235         .instruction(fetch_output_instruction),
 236         .funct7(decoder_funct7),
 237         .funct3(decoder_funct3),
 238         .rd(decoder_rd),
 239         .rs1(decoder_rs1),
 240         .rs2(decoder_rs2),
 241         .immediate(decoder_immediate),
 242         .opcode(decoder_opcode),
 243         .decode_action(decode_action));
 244
 245     wire [31:0] register_rs1 = (decoder_rs1 == 0) ? 0 : registers[decoder_rs1];
 246     wire [31:0] register_rs2 = (decoder_rs2 == 0) ? 0 : registers[decoder_rs2];
 247
 248     wire [31:0] load_store_address = decoder_immediate + register_rs1;
 249
 250     wire [1:0] load_store_address_low_2 = decoder_immediate[1:0] + register_rs1[1:0];
 251
 252     function get_load_store_misaligned(
 253         input [2:0] funct3,
 254         input [1:0] load_store_address_low_2
 255         );
 256     begin
 257         case(funct3[1:0])
 258         `funct3_sb:
 259             get_load_store_misaligned = 0;
 260         `funct3_sh:
 261             get_load_store_misaligned = load_store_address_low_2[0] != 0;
 262         `funct3_sw:
 263             get_load_store_misaligned = load_store_address_low_2[1:0] != 0;
 264         default:
 265             get_load_store_misaligned = 1'bX;
 266         endcase
 267     end
 268     endfunction
 269
 270     wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2);
 271
 272     assign memory_interface_rw_address = load_store_address[31:2];
 273
 274     wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
 275
 276     assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
 277
 278     assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
 279                                                 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
 280                                                 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
 281     assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
 282     assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
 283     assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
 284
 285     wire [31:0] unmasked_loaded_value;
 286
 287     assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
 288                                         ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
 289                                         : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
 290     assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
 291     assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
 292
 293     wire [31:0] loaded_value;
 294
 295     assign loaded_value[7:0] = unmasked_loaded_value[7:0];
 296     assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
 297     assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
 298
 299     assign memory_interface_rw_active = ~reset
 300                                         & (fetch_output_state == `fetch_output_state_valid)
 301                                         & ~load_store_misaligned
 302                                         & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
 303
 304     assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
 305
 306     wire [31:0] alu_a = register_rs1;
 307     wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
 308     wire [31:0] alu_result;
 309
 310     cpu_alu alu(
 311         .funct7(decoder_funct7),
 312         .funct3(decoder_funct3),
 313         .opcode(decoder_opcode),
 314         .a(alu_a),
 315         .b(alu_b),
 316         .result(alu_result)
 317         );
 318
 319     wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
 320
 321     assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
 322     assign fetch_target_pc[0] = 0;
 323
 324     wire misaligned_jump_target = fetch_target_pc[1];
 325
 326     wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
 327     wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
 328
 329     wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
 330
 331     reg [31:0] mcause = 0;
 332     reg [31:0] mepc = 32'hXXXXXXXX;
 333     reg [31:0] mscratch = 32'hXXXXXXXX;
 334
 335     reg mstatus_mpie = 1'bX;
 336     reg mstatus_mie = 0;
 337     parameter mstatus_mprv = 0;
 338     parameter mstatus_tsr = 0;
 339     parameter mstatus_tw = 0;
 340     parameter mstatus_tvm = 0;
 341     parameter mstatus_mxr = 0;
 342     parameter mstatus_sum = 0;
 343     parameter mstatus_xs = 0;
 344     parameter mstatus_fs = 0;
 345     parameter mstatus_mpp = 2'b11;
 346     parameter mstatus_spp = 0;
 347     parameter mstatus_spie = 0;
 348     parameter mstatus_upie = 0;
 349     parameter mstatus_sie = 0;
 350     parameter mstatus_uie = 0;
 351
 352     reg mie_meie = 1'bX;
 353     reg mie_mtie = 1'bX;
 354     reg mie_msie = 1'bX;
 355     parameter mie_seie = 0;
 356     parameter mie_ueie = 0;
 357     parameter mie_stie = 0;
 358     parameter mie_utie = 0;
 359     parameter mie_ssie = 0;
 360     parameter mie_usie = 0;
 361
 362     task reset_to_initial;
 363     begin
 364         mcause = 0;
 365         mepc = 32'hXXXXXXXX;
 366         mscratch = 32'hXXXXXXXX;
 367         mstatus_mie = 0;
 368         mstatus_mpie = 1'bX;
 369         mie_meie = 1'bX;
 370         mie_mtie = 1'bX;
 371         mie_msie = 1'bX;
 372         registers['h01] <= 32'hXXXXXXXX;
 373         registers['h02] <= 32'hXXXXXXXX;
 374         registers['h03] <= 32'hXXXXXXXX;
 375         registers['h04] <= 32'hXXXXXXXX;
 376         registers['h05] <= 32'hXXXXXXXX;
 377         registers['h06] <= 32'hXXXXXXXX;
 378         registers['h07] <= 32'hXXXXXXXX;
 379         registers['h08] <= 32'hXXXXXXXX;
 380         registers['h09] <= 32'hXXXXXXXX;
 381         registers['h0A] <= 32'hXXXXXXXX;
 382         registers['h0B] <= 32'hXXXXXXXX;
 383         registers['h0C] <= 32'hXXXXXXXX;
 384         registers['h0D] <= 32'hXXXXXXXX;
 385         registers['h0E] <= 32'hXXXXXXXX;
 386         registers['h0F] <= 32'hXXXXXXXX;
 387         registers['h10] <= 32'hXXXXXXXX;
 388         registers['h11] <= 32'hXXXXXXXX;
 389         registers['h12] <= 32'hXXXXXXXX;
 390         registers['h13] <= 32'hXXXXXXXX;
 391         registers['h14] <= 32'hXXXXXXXX;
 392         registers['h15] <= 32'hXXXXXXXX;
 393         registers['h16] <= 32'hXXXXXXXX;
 394         registers['h17] <= 32'hXXXXXXXX;
 395         registers['h18] <= 32'hXXXXXXXX;
 396         registers['h19] <= 32'hXXXXXXXX;
 397         registers['h1A] <= 32'hXXXXXXXX;
 398         registers['h1B] <= 32'hXXXXXXXX;
 399         registers['h1C] <= 32'hXXXXXXXX;
 400         registers['h1D] <= 32'hXXXXXXXX;
 401         registers['h1E] <= 32'hXXXXXXXX;
 402         registers['h1F] <= 32'hXXXXXXXX;
 403     end
 404     endtask
 405
 406     task write_register(input [4:0] register_number, input [31:0] value);
 407     begin
 408         if(register_number != 0)
 409             registers[register_number] <= value;
 410     end
 411     endtask
 412
 413     function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
 414     begin
 415         case(funct3)
 416         `funct3_csrrw, `funct3_csrrwi:
 417             evaluate_csr_funct3_operation = written_value;
 418         `funct3_csrrs, `funct3_csrrsi:
 419             evaluate_csr_funct3_operation = written_value | previous_value;
 420         `funct3_csrrc, `funct3_csrrci:
 421             evaluate_csr_funct3_operation = ~written_value & previous_value;
 422         default:
 423             evaluate_csr_funct3_operation = 32'hXXXXXXXX;
 424         endcase
 425     end
 426     endfunction
 427
 428     parameter misa_a = 1'b0;
 429     parameter misa_b = 1'b0;
 430     parameter misa_c = 1'b0;
 431     parameter misa_d = 1'b0;
 432     parameter misa_e = 1'b0;
 433     parameter misa_f = 1'b0;
 434     parameter misa_g = 1'b0;
 435     parameter misa_h = 1'b0;
 436     parameter misa_i = 1'b1;
 437     parameter misa_j = 1'b0;
 438     parameter misa_k = 1'b0;
 439     parameter misa_l = 1'b0;
 440     parameter misa_m = 1'b0;
 441     parameter misa_n = 1'b0;
 442     parameter misa_o = 1'b0;
 443     parameter misa_p = 1'b0;
 444     parameter misa_q = 1'b0;
 445     parameter misa_r = 1'b0;
 446     parameter misa_s = 1'b0;
 447     parameter misa_t = 1'b0;
 448     parameter misa_u = 1'b0;
 449     parameter misa_v = 1'b0;
 450     parameter misa_w = 1'b0;
 451     parameter misa_x = 1'b0;
 452     parameter misa_y = 1'b0;
 453     parameter misa_z = 1'b0;
 454     parameter misa = {
 455         2'b01,
 456         4'b0,
 457         misa_z,
 458         misa_y,
 459         misa_x,
 460         misa_w,
 461         misa_v,
 462         misa_u,
 463         misa_t,
 464         misa_s,
 465         misa_r,
 466         misa_q,
 467         misa_p,
 468         misa_o,
 469         misa_n,
 470         misa_m,
 471         misa_l,
 472         misa_k,
 473         misa_j,
 474         misa_i,
 475         misa_h,
 476         misa_g,
 477         misa_f,
 478         misa_e,
 479         misa_d,
 480         misa_c,
 481         misa_b,
 482         misa_a};
 483
 484     parameter mvendorid = 32'b0;
 485     parameter marchid = 32'b0;
 486     parameter mimpid = 32'b0;
 487     parameter mhartid = 32'b0;
 488
 489     function [31:0] make_mstatus(input mstatus_tsr,
 490         input mstatus_tw,
 491         input mstatus_tvm,
 492         input mstatus_mxr,
 493         input mstatus_sum,
 494         input mstatus_mprv,
 495         input [1:0] mstatus_xs,
 496         input [1:0] mstatus_fs,
 497         input [1:0] mstatus_mpp,
 498         input mstatus_spp,
 499         input mstatus_mpie,
 500         input mstatus_spie,
 501         input mstatus_upie,
 502         input mstatus_mie,
 503         input mstatus_sie,
 504         input mstatus_uie);
 505     begin
 506         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 507             8'b0,
 508             mstatus_tsr,
 509             mstatus_tw,
 510             mstatus_tvm,
 511             mstatus_mxr,
 512             mstatus_sum,
 513             mstatus_mprv,
 514             mstatus_xs,
 515             mstatus_fs,
 516             mstatus_mpp,
 517             2'b0,
 518             mstatus_spp,
 519             mstatus_mpie,
 520             1'b0,
 521             mstatus_spie,
 522             mstatus_upie,
 523             mstatus_mie,
 524             1'b0,
 525             mstatus_sie,
 526             mstatus_uie};
 527     end
 528     endfunction
 529
 530     wire mip_meip = 0; // TODO: implement external interrupts
 531     parameter mip_seip = 0;
 532     parameter mip_ueip = 0;
 533     wire mip_mtip = 0; // TODO: implement timer interrupts
 534     parameter mip_stip = 0;
 535     parameter mip_utip = 0;
 536     parameter mip_msip = 0;
 537     parameter mip_ssip = 0;
 538     parameter mip_usip = 0;
 539
 540     wire csr_op_is_valid;
 541
 542     function `fetch_action get_fetch_action(
 543         input `fetch_output_state fetch_output_state,
 544         input `decode_action decode_action,
 545         input load_store_misaligned,
 546         input memory_interface_rw_address_valid,
 547         input memory_interface_rw_wait,
 548         input branch_taken,
 549         input misaligned_jump_target,
 550         input csr_op_is_valid
 551         );
 552     begin
 553         case(fetch_output_state)
 554         `fetch_output_state_empty:
 555             get_fetch_action = `fetch_action_default;
 556         `fetch_output_state_trap:
 557             get_fetch_action = `fetch_action_ack_trap;
 558         `fetch_output_state_valid: begin
 559             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 560                 get_fetch_action = `fetch_action_error_trap;
 561             end
 562             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 563                 get_fetch_action = `fetch_action_noerror_trap;
 564             end
 565             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 566                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 567                     get_fetch_action = `fetch_action_error_trap;
 568                 end
 569                 else if(memory_interface_rw_wait) begin
 570                     get_fetch_action = `fetch_action_wait;
 571                 end
 572                 else begin
 573                     get_fetch_action = `fetch_action_default;
 574                 end
 575             end
 576             else if((decode_action & `decode_action_fence_i) != 0) begin
 577                 get_fetch_action = `fetch_action_fence;
 578             end
 579             else if((decode_action & `decode_action_branch) != 0) begin
 580                 if(branch_taken) begin
 581                     if(misaligned_jump_target) begin
 582                         get_fetch_action = `fetch_action_error_trap;
 583                     end
 584                     else begin
 585                         get_fetch_action = `fetch_action_jump;
 586                     end
 587                 end
 588                 else
 589                 begin
 590                     get_fetch_action = `fetch_action_default;
 591                 end
 592             end
 593             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 594                 if(misaligned_jump_target) begin
 595                     get_fetch_action = `fetch_action_error_trap;
 596                 end
 597                 else begin
 598                     get_fetch_action = `fetch_action_jump;
 599                 end
 600             end
 601             else if((decode_action & `decode_action_csr) != 0) begin
 602                 if(csr_op_is_valid)
 603                     get_fetch_action = `fetch_action_default;
 604                 else
 605                     get_fetch_action = `fetch_action_error_trap;
 606             end
 607             else begin
 608                 get_fetch_action = `fetch_action_default;
 609             end
 610         end
 611         default:
 612             get_fetch_action = 32'hXXXXXXXX;
 613         endcase
 614     end
 615     endfunction
 616
 617     assign fetch_action = get_fetch_action(
 618         fetch_output_state,
 619         decode_action,
 620         load_store_misaligned,
 621         memory_interface_rw_address_valid,
 622         memory_interface_rw_wait,
 623         branch_taken,
 624         misaligned_jump_target,
 625         csr_op_is_valid
 626         );
 627
 628     task handle_trap;
 629     begin
 630         mstatus_mpie = mstatus_mie;
 631         mstatus_mie = 0;
 632         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 633         if(fetch_action == `fetch_action_ack_trap) begin
 634             mcause = `cause_instruction_access_fault;
 635         end
 636         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 637             mcause = `cause_illegal_instruction;
 638         end
 639         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 640             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 641         end
 642         else if((decode_action & `decode_action_load) != 0) begin
 643             if(load_store_misaligned)
 644                 mcause = `cause_load_address_misaligned;
 645             else
 646                 mcause = `cause_load_access_fault;
 647         end
 648         else if((decode_action & `decode_action_store) != 0) begin
 649             if(load_store_misaligned)
 650                 mcause = `cause_store_amo_address_misaligned;
 651             else
 652                 mcause = `cause_store_amo_access_fault;
 653         end
 654         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 655             mcause = `cause_instruction_address_misaligned;
 656         end
 657         else begin
 658             mcause = `cause_illegal_instruction;
 659         end
 660     end
 661     endtask
 662
 663     wire [11:0] csr_number = decoder_immediate;
 664     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 665     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 666     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 667
 668     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 669     begin
 670         case(csr_number)
 671         `csr_ustatus,
 672         `csr_fflags,
 673         `csr_frm,
 674         `csr_fcsr,
 675         `csr_uie,
 676         `csr_utvec,
 677         `csr_uscratch,
 678         `csr_uepc,
 679         `csr_ucause,
 680         `csr_utval,
 681         `csr_uip,
 682         `csr_sstatus,
 683         `csr_sedeleg,
 684         `csr_sideleg,
 685         `csr_sie,
 686         `csr_stvec,
 687         `csr_scounteren,
 688         `csr_sscratch,
 689         `csr_sepc,
 690         `csr_scause,
 691         `csr_stval,
 692         `csr_sip,
 693         `csr_satp,
 694         `csr_medeleg,
 695         `csr_mideleg,
 696         `csr_dcsr,
 697         `csr_dpc,
 698         `csr_dscratch:
 699             get_csr_op_is_valid = 0;
 700         `csr_cycle,
 701         `csr_time,
 702         `csr_instret,
 703         `csr_cycleh,
 704         `csr_timeh,
 705         `csr_instreth,
 706         `csr_mvendorid,
 707         `csr_marchid,
 708         `csr_mimpid,
 709         `csr_mhartid:
 710             get_csr_op_is_valid = ~csr_writes;
 711         `csr_misa,
 712         `csr_mstatus,
 713         `csr_mie,
 714         `csr_mtvec,
 715         `csr_mscratch,
 716         `csr_mepc,
 717         `csr_mcause,
 718         `csr_mip:
 719             get_csr_op_is_valid = 1;
 720         `csr_mcounteren,
 721         `csr_mtval,
 722         `csr_mcycle,
 723         `csr_minstret,
 724         `csr_mcycleh,
 725         `csr_minstreth:
 726             // TODO: CSRs not implemented yet
 727             get_csr_op_is_valid = 0;
 728         endcase
 729     end
 730     endfunction
 731
 732     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 733
 734     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 735     wire [63:0] time_counter = 0; // TODO: implement time_counter
 736     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 737
 738     always @(posedge clk) begin:main_block
 739         if(reset) begin
 740             reset_to_initial();
 741             disable main_block;
 742         end
 743         case(fetch_output_state)
 744         `fetch_output_state_empty: begin
 745         end
 746         `fetch_output_state_trap: begin
 747             handle_trap();
 748         end
 749         `fetch_output_state_valid: begin:valid
 750             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 751                 handle_trap();
 752             end
 753             else if((decode_action & `decode_action_load) != 0) begin
 754                 if(~memory_interface_rw_wait)
 755                     write_register(decoder_rd, loaded_value);
 756             end
 757             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 758                 write_register(decoder_rd, alu_result);
 759             end
 760             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 761                 write_register(decoder_rd, lui_auipc_result);
 762             end
 763             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 764                 write_register(decoder_rd, fetch_output_pc + 4);
 765             end
 766             else if((decode_action & `decode_action_csr) != 0) begin:csr
 767                 reg [31:0] csr_output_value;
 768                 reg [31:0] csr_written_value;
 769                 csr_output_value = 32'hXXXXXXXX;
 770                 csr_written_value = 32'hXXXXXXXX;
 771                 case(csr_number)
 772                 `csr_cycle: begin
 773                     csr_output_value = cycle_counter[31:0];
 774                 end
 775                 `csr_time: begin
 776                     csr_output_value = time_counter[31:0];
 777                 end
 778                 `csr_instret: begin
 779                     csr_output_value = instret_counter[31:0];
 780                 end
 781                 `csr_cycleh: begin
 782                     csr_output_value = cycle_counter[63:32];
 783                 end
 784                 `csr_timeh: begin
 785                     csr_output_value = time_counter[63:32];
 786                 end
 787                 `csr_instreth: begin
 788                     csr_output_value = instret_counter[63:32];
 789                 end
 790                 `csr_mvendorid: begin
 791                     csr_output_value = mvendorid;
 792                 end
 793                 `csr_marchid: begin
 794                     csr_output_value = marchid;
 795                 end
 796                 `csr_mimpid: begin
 797                     csr_output_value = mimpid;
 798                 end
 799                 `csr_mhartid: begin
 800                     csr_output_value = mhartid;
 801                 end
 802                 `csr_misa: begin
 803                     csr_output_value = misa;
 804                 end
 805                 `csr_mstatus: begin
 806                     csr_output_value = make_mstatus(mstatus_tsr,
 807                                                     mstatus_tw,
 808                                                     mstatus_tvm,
 809                                                     mstatus_mxr,
 810                                                     mstatus_sum,
 811                                                     mstatus_mprv,
 812                                                     mstatus_xs,
 813                                                     mstatus_fs,
 814                                                     mstatus_mpp,
 815                                                     mstatus_spp,
 816                                                     mstatus_mpie,
 817                                                     mstatus_spie,
 818                                                     mstatus_upie,
 819                                                     mstatus_mie,
 820                                                     mstatus_sie,
 821                                                     mstatus_uie);
 822                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 823                     if(csr_writes) begin
 824                         mstatus_mpie = csr_written_value[7];
 825                         mstatus_mie = csr_written_value[3];
 826                     end
 827                 end
 828                 `csr_mie: begin
 829                     csr_output_value = 0;
 830                     csr_output_value[11] = mie_meie;
 831                     csr_output_value[9] = mie_seie;
 832                     csr_output_value[8] = mie_ueie;
 833                     csr_output_value[7] = mie_mtie;
 834                     csr_output_value[5] = mie_stie;
 835                     csr_output_value[4] = mie_utie;
 836                     csr_output_value[3] = mie_msie;
 837                     csr_output_value[1] = mie_ssie;
 838                     csr_output_value[0] = mie_usie;
 839                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 840                     if(csr_writes) begin
 841                         mie_meie = csr_written_value[11];
 842                         mie_mtie = csr_written_value[7];
 843                         mie_msie = csr_written_value[3];
 844                     end
 845                 end
 846                 `csr_mtvec: begin
 847                     csr_output_value = mtvec;
 848                 end
 849                 `csr_mscratch: begin
 850                     csr_output_value = mscratch;
 851                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 852                     if(csr_writes)
 853                         mscratch = csr_written_value;
 854                 end
 855                 `csr_mepc: begin
 856                     csr_output_value = mepc;
 857                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 858                     if(csr_writes)
 859                         mepc = csr_written_value;
 860                 end
 861                 `csr_mcause: begin
 862                     csr_output_value = mcause;
 863                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 864                     if(csr_writes)
 865                         mcause = csr_written_value;
 866                 end
 867                 `csr_mip: begin
 868                     csr_output_value = 0;
 869                     csr_output_value[11] = mip_meip;
 870                     csr_output_value[9] = mip_seip;
 871                     csr_output_value[8] = mip_ueip;
 872                     csr_output_value[7] = mip_mtip;
 873                     csr_output_value[5] = mip_stip;
 874                     csr_output_value[4] = mip_utip;
 875                     csr_output_value[3] = mip_msip;
 876                     csr_output_value[1] = mip_ssip;
 877                     csr_output_value[0] = mip_usip;
 878                 end
 879                 endcase
 880                 if(csr_reads)
 881                     write_register(decoder_rd, csr_output_value);
 882             end
 883             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 884                 // do nothing
 885             end
 886         end
 887         endcase
 888     end
 889
 890 endmodule
 891 """
 892