3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 from migen
.fhdl
import verilog
32 from riscvdefs
import *
40 #self.clk = ClockSignal()
41 #self.reset = ResetSignal()
42 self
.tty_write
= Signal()
43 self
.tty_write_data
= Signal(8)
44 self
.tty_write_busy
= Signal()
45 self
.switch_2
= Signal()
46 self
.switch_3
= Signal()
50 ram_size
= Constant(0x8000)
51 ram_start
= Constant(0x10000, 32)
52 reset_vector
= Signal(32)
55 reset_vector
.eq(ram_start
)
56 mtvec
.eq(ram_start
+ 0x40)
60 l
.append(Signal(32, name
="register%d" % i
))
61 self
.registers
= Array(l
)
63 #self.sync += self.registers[0].eq(0)
64 #self.sync += self.registers[1].eq(0)
66 memory_interface_fetch_address
= Signal(32)[2:]
67 memory_interface_fetch_data
= Signal(32)
68 memory_interface_fetch_valid
= Signal()
69 memory_interface_rw_address
= Signal(32)[2:]
70 memory_interface_rw_byte_mask
= Signal(4)
71 memory_interface_rw_read_not_write
= Signal()
72 memory_interface_rw_active
= Signal()
73 memory_interface_rw_data_in
= Signal(32)
74 memory_interface_rw_data_out
= Signal(32)
75 memory_interface_rw_address_valid
= Signal()
76 memory_interface_rw_wait
= Signal()
78 mi
= Instance("cpu_memory_interface",
79 p_ram_size
= ram_size
,
80 p_ram_start
= ram_start
,
83 i_fetch_address
= memory_interface_fetch_address
,
84 o_fetch_data
= memory_interface_fetch_data
,
85 o_fetch_valid
= memory_interface_fetch_valid
,
86 i_rw_address
= memory_interface_rw_address
,
87 i_rw_byte_mask
= memory_interface_rw_byte_mask
,
88 i_rw_read_not_write
= memory_interface_rw_read_not_write
,
89 i_rw_active
= memory_interface_rw_active
,
90 i_rw_data_in
= memory_interface_rw_data_in
,
91 o_rw_data_out
= memory_interface_rw_data_out
,
92 o_rw_address_valid
= memory_interface_rw_address_valid
,
93 o_rw_wait
= memory_interface_rw_wait
,
94 o_tty_write
= self
.tty_write
,
95 o_tty_write_data
= self
.tty_write_data
,
96 i_tty_write_busy
= self
.tty_write_busy
,
97 i_switch_2
= self
.switch_2
,
98 i_switch_3
= self
.switch_3
,
105 cpu_memory_interface #(
107 .ram_start(ram_start)
111 .fetch_address(memory_interface_fetch_address),
112 .fetch_data(memory_interface_fetch_data),
113 .fetch_valid(memory_interface_fetch_valid),
114 .rw_address(memory_interface_rw_address),
115 .rw_byte_mask(memory_interface_rw_byte_mask),
116 .rw_read_not_write(memory_interface_rw_read_not_write),
117 .rw_active(memory_interface_rw_active),
118 .rw_data_in(memory_interface_rw_data_in),
119 .rw_data_out(memory_interface_rw_data_out),
120 .rw_address_valid(memory_interface_rw_address_valid),
121 .rw_wait(memory_interface_rw_wait),
122 .tty_write(tty_write),
123 .tty_write_data(tty_write_data),
124 .tty_write_busy(tty_write_busy),
132 if __name__
== "__main__":
134 print(verilog
.convert(example
,
137 example
.tty_write_data
,
138 example
.tty_write_busy
,
150 output [7:0] tty_write_data,
151 input tty_write_busy,
158 parameter ram_size = 'h8000;
159 parameter ram_start = 32'h1_0000;
160 parameter reset_vector = ram_start;
161 parameter mtvec = ram_start + 'h40;
163 reg [31:0] registers[31:1];
165 wire [31:2] memory_interface_fetch_address;
166 wire [31:0] memory_interface_fetch_data;
167 wire memory_interface_fetch_valid;
168 wire [31:2] memory_interface_rw_address;
169 wire [3:0] memory_interface_rw_byte_mask;
170 wire memory_interface_rw_read_not_write;
171 wire memory_interface_rw_active;
172 wire [31:0] memory_interface_rw_data_in;
173 wire [31:0] memory_interface_rw_data_out;
174 wire memory_interface_rw_address_valid;
175 wire memory_interface_rw_wait;
177 cpu_memory_interface #(
179 .ram_start(ram_start)
183 .fetch_address(memory_interface_fetch_address),
184 .fetch_data(memory_interface_fetch_data),
185 .fetch_valid(memory_interface_fetch_valid),
186 .rw_address(memory_interface_rw_address),
187 .rw_byte_mask(memory_interface_rw_byte_mask),
188 .rw_read_not_write(memory_interface_rw_read_not_write),
189 .rw_active(memory_interface_rw_active),
190 .rw_data_in(memory_interface_rw_data_in),
191 .rw_data_out(memory_interface_rw_data_out),
192 .rw_address_valid(memory_interface_rw_address_valid),
193 .rw_wait(memory_interface_rw_wait),
194 .tty_write(tty_write),
195 .tty_write_data(tty_write_data),
196 .tty_write_busy(tty_write_busy),
203 wire `fetch_action fetch_action;
204 wire [31:0] fetch_target_pc;
205 wire [31:0] fetch_output_pc;
206 wire [31:0] fetch_output_instruction;
207 wire `fetch_output_state fetch_output_state;
210 .reset_vector(reset_vector),
215 .memory_interface_fetch_address(memory_interface_fetch_address),
216 .memory_interface_fetch_data(memory_interface_fetch_data),
217 .memory_interface_fetch_valid(memory_interface_fetch_valid),
218 .fetch_action(fetch_action),
219 .target_pc(fetch_target_pc),
220 .output_pc(fetch_output_pc),
221 .output_instruction(fetch_output_instruction),
222 .output_state(fetch_output_state)
225 wire [6:0] decoder_funct7;
226 wire [2:0] decoder_funct3;
227 wire [4:0] decoder_rd;
228 wire [4:0] decoder_rs1;
229 wire [4:0] decoder_rs2;
230 wire [31:0] decoder_immediate;
231 wire [6:0] decoder_opcode;
232 wire `decode_action decode_action;
235 .instruction(fetch_output_instruction),
236 .funct7(decoder_funct7),
237 .funct3(decoder_funct3),
241 .immediate(decoder_immediate),
242 .opcode(decoder_opcode),
243 .decode_action(decode_action));
245 wire [31:0] register_rs1 = (decoder_rs1 == 0) ? 0 : registers[decoder_rs1];
246 wire [31:0] register_rs2 = (decoder_rs2 == 0) ? 0 : registers[decoder_rs2];
248 wire [31:0] load_store_address = decoder_immediate + register_rs1;
250 wire [1:0] load_store_address_low_2 = decoder_immediate[1:0] + register_rs1[1:0];
252 function get_load_store_misaligned(
254 input [1:0] load_store_address_low_2
259 get_load_store_misaligned = 0;
261 get_load_store_misaligned = load_store_address_low_2[0] != 0;
263 get_load_store_misaligned = load_store_address_low_2[1:0] != 0;
265 get_load_store_misaligned = 1'bX;
270 wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2);
272 assign memory_interface_rw_address = load_store_address[31:2];
274 wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
276 assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
278 assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
279 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
280 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
281 assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
282 assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
283 assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
285 wire [31:0] unmasked_loaded_value;
287 assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
288 ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
289 : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
290 assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
291 assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
293 wire [31:0] loaded_value;
295 assign loaded_value[7:0] = unmasked_loaded_value[7:0];
296 assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
297 assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
299 assign memory_interface_rw_active = ~reset
300 & (fetch_output_state == `fetch_output_state_valid)
301 & ~load_store_misaligned
302 & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
304 assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
306 wire [31:0] alu_a = register_rs1;
307 wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
308 wire [31:0] alu_result;
311 .funct7(decoder_funct7),
312 .funct3(decoder_funct3),
313 .opcode(decoder_opcode),
319 wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
321 assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
322 assign fetch_target_pc[0] = 0;
324 wire misaligned_jump_target = fetch_target_pc[1];
326 wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
327 wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
329 wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
331 reg [31:0] mcause = 0;
332 reg [31:0] mepc = 32'hXXXXXXXX;
333 reg [31:0] mscratch = 32'hXXXXXXXX;
335 reg mstatus_mpie = 1'bX;
337 parameter mstatus_mprv = 0;
338 parameter mstatus_tsr = 0;
339 parameter mstatus_tw = 0;
340 parameter mstatus_tvm = 0;
341 parameter mstatus_mxr = 0;
342 parameter mstatus_sum = 0;
343 parameter mstatus_xs = 0;
344 parameter mstatus_fs = 0;
345 parameter mstatus_mpp = 2'b11;
346 parameter mstatus_spp = 0;
347 parameter mstatus_spie = 0;
348 parameter mstatus_upie = 0;
349 parameter mstatus_sie = 0;
350 parameter mstatus_uie = 0;
355 parameter mie_seie = 0;
356 parameter mie_ueie = 0;
357 parameter mie_stie = 0;
358 parameter mie_utie = 0;
359 parameter mie_ssie = 0;
360 parameter mie_usie = 0;
362 task reset_to_initial;
366 mscratch = 32'hXXXXXXXX;
372 registers['h01] <= 32'hXXXXXXXX;
373 registers['h02] <= 32'hXXXXXXXX;
374 registers['h03] <= 32'hXXXXXXXX;
375 registers['h04] <= 32'hXXXXXXXX;
376 registers['h05] <= 32'hXXXXXXXX;
377 registers['h06] <= 32'hXXXXXXXX;
378 registers['h07] <= 32'hXXXXXXXX;
379 registers['h08] <= 32'hXXXXXXXX;
380 registers['h09] <= 32'hXXXXXXXX;
381 registers['h0A] <= 32'hXXXXXXXX;
382 registers['h0B] <= 32'hXXXXXXXX;
383 registers['h0C] <= 32'hXXXXXXXX;
384 registers['h0D] <= 32'hXXXXXXXX;
385 registers['h0E] <= 32'hXXXXXXXX;
386 registers['h0F] <= 32'hXXXXXXXX;
387 registers['h10] <= 32'hXXXXXXXX;
388 registers['h11] <= 32'hXXXXXXXX;
389 registers['h12] <= 32'hXXXXXXXX;
390 registers['h13] <= 32'hXXXXXXXX;
391 registers['h14] <= 32'hXXXXXXXX;
392 registers['h15] <= 32'hXXXXXXXX;
393 registers['h16] <= 32'hXXXXXXXX;
394 registers['h17] <= 32'hXXXXXXXX;
395 registers['h18] <= 32'hXXXXXXXX;
396 registers['h19] <= 32'hXXXXXXXX;
397 registers['h1A] <= 32'hXXXXXXXX;
398 registers['h1B] <= 32'hXXXXXXXX;
399 registers['h1C] <= 32'hXXXXXXXX;
400 registers['h1D] <= 32'hXXXXXXXX;
401 registers['h1E] <= 32'hXXXXXXXX;
402 registers['h1F] <= 32'hXXXXXXXX;
406 task write_register(input [4:0] register_number, input [31:0] value);
408 if(register_number != 0)
409 registers[register_number] <= value;
413 function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
416 `funct3_csrrw, `funct3_csrrwi:
417 evaluate_csr_funct3_operation = written_value;
418 `funct3_csrrs, `funct3_csrrsi:
419 evaluate_csr_funct3_operation = written_value | previous_value;
420 `funct3_csrrc, `funct3_csrrci:
421 evaluate_csr_funct3_operation = ~written_value & previous_value;
423 evaluate_csr_funct3_operation = 32'hXXXXXXXX;
428 parameter misa_a = 1'b0;
429 parameter misa_b = 1'b0;
430 parameter misa_c = 1'b0;
431 parameter misa_d = 1'b0;
432 parameter misa_e = 1'b0;
433 parameter misa_f = 1'b0;
434 parameter misa_g = 1'b0;
435 parameter misa_h = 1'b0;
436 parameter misa_i = 1'b1;
437 parameter misa_j = 1'b0;
438 parameter misa_k = 1'b0;
439 parameter misa_l = 1'b0;
440 parameter misa_m = 1'b0;
441 parameter misa_n = 1'b0;
442 parameter misa_o = 1'b0;
443 parameter misa_p = 1'b0;
444 parameter misa_q = 1'b0;
445 parameter misa_r = 1'b0;
446 parameter misa_s = 1'b0;
447 parameter misa_t = 1'b0;
448 parameter misa_u = 1'b0;
449 parameter misa_v = 1'b0;
450 parameter misa_w = 1'b0;
451 parameter misa_x = 1'b0;
452 parameter misa_y = 1'b0;
453 parameter misa_z = 1'b0;
484 parameter mvendorid = 32'b0;
485 parameter marchid = 32'b0;
486 parameter mimpid = 32'b0;
487 parameter mhartid = 32'b0;
489 function [31:0] make_mstatus(input mstatus_tsr,
495 input [1:0] mstatus_xs,
496 input [1:0] mstatus_fs,
497 input [1:0] mstatus_mpp,
506 make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
530 wire mip_meip = 0; // TODO: implement external interrupts
531 parameter mip_seip = 0;
532 parameter mip_ueip = 0;
533 wire mip_mtip = 0; // TODO: implement timer interrupts
534 parameter mip_stip = 0;
535 parameter mip_utip = 0;
536 parameter mip_msip = 0;
537 parameter mip_ssip = 0;
538 parameter mip_usip = 0;
540 wire csr_op_is_valid;
542 function `fetch_action get_fetch_action(
543 input `fetch_output_state fetch_output_state,
544 input `decode_action decode_action,
545 input load_store_misaligned,
546 input memory_interface_rw_address_valid,
547 input memory_interface_rw_wait,
549 input misaligned_jump_target,
550 input csr_op_is_valid
553 case(fetch_output_state)
554 `fetch_output_state_empty:
555 get_fetch_action = `fetch_action_default;
556 `fetch_output_state_trap:
557 get_fetch_action = `fetch_action_ack_trap;
558 `fetch_output_state_valid: begin
559 if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
560 get_fetch_action = `fetch_action_error_trap;
562 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
563 get_fetch_action = `fetch_action_noerror_trap;
565 else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
566 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
567 get_fetch_action = `fetch_action_error_trap;
569 else if(memory_interface_rw_wait) begin
570 get_fetch_action = `fetch_action_wait;
573 get_fetch_action = `fetch_action_default;
576 else if((decode_action & `decode_action_fence_i) != 0) begin
577 get_fetch_action = `fetch_action_fence;
579 else if((decode_action & `decode_action_branch) != 0) begin
580 if(branch_taken) begin
581 if(misaligned_jump_target) begin
582 get_fetch_action = `fetch_action_error_trap;
585 get_fetch_action = `fetch_action_jump;
590 get_fetch_action = `fetch_action_default;
593 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
594 if(misaligned_jump_target) begin
595 get_fetch_action = `fetch_action_error_trap;
598 get_fetch_action = `fetch_action_jump;
601 else if((decode_action & `decode_action_csr) != 0) begin
603 get_fetch_action = `fetch_action_default;
605 get_fetch_action = `fetch_action_error_trap;
608 get_fetch_action = `fetch_action_default;
612 get_fetch_action = 32'hXXXXXXXX;
617 assign fetch_action = get_fetch_action(
620 load_store_misaligned,
621 memory_interface_rw_address_valid,
622 memory_interface_rw_wait,
624 misaligned_jump_target,
630 mstatus_mpie = mstatus_mie;
632 mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
633 if(fetch_action == `fetch_action_ack_trap) begin
634 mcause = `cause_instruction_access_fault;
636 else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
637 mcause = `cause_illegal_instruction;
639 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
640 mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
642 else if((decode_action & `decode_action_load) != 0) begin
643 if(load_store_misaligned)
644 mcause = `cause_load_address_misaligned;
646 mcause = `cause_load_access_fault;
648 else if((decode_action & `decode_action_store) != 0) begin
649 if(load_store_misaligned)
650 mcause = `cause_store_amo_address_misaligned;
652 mcause = `cause_store_amo_access_fault;
654 else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
655 mcause = `cause_instruction_address_misaligned;
658 mcause = `cause_illegal_instruction;
663 wire [11:0] csr_number = decoder_immediate;
664 wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
665 wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
666 wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
668 function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
699 get_csr_op_is_valid = 0;
710 get_csr_op_is_valid = ~csr_writes;
719 get_csr_op_is_valid = 1;
726 // TODO: CSRs not implemented yet
727 get_csr_op_is_valid = 0;
732 assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
734 wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
735 wire [63:0] time_counter = 0; // TODO: implement time_counter
736 wire [63:0] instret_counter = 0; // TODO: implement instret_counter
738 always @(posedge clk) begin:main_block
743 case(fetch_output_state)
744 `fetch_output_state_empty: begin
746 `fetch_output_state_trap: begin
749 `fetch_output_state_valid: begin:valid
750 if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
753 else if((decode_action & `decode_action_load) != 0) begin
754 if(~memory_interface_rw_wait)
755 write_register(decoder_rd, loaded_value);
757 else if((decode_action & `decode_action_op_op_imm) != 0) begin
758 write_register(decoder_rd, alu_result);
760 else if((decode_action & `decode_action_lui_auipc) != 0) begin
761 write_register(decoder_rd, lui_auipc_result);
763 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
764 write_register(decoder_rd, fetch_output_pc + 4);
766 else if((decode_action & `decode_action_csr) != 0) begin:csr
767 reg [31:0] csr_output_value;
768 reg [31:0] csr_written_value;
769 csr_output_value = 32'hXXXXXXXX;
770 csr_written_value = 32'hXXXXXXXX;
773 csr_output_value = cycle_counter[31:0];
776 csr_output_value = time_counter[31:0];
779 csr_output_value = instret_counter[31:0];
782 csr_output_value = cycle_counter[63:32];
785 csr_output_value = time_counter[63:32];
788 csr_output_value = instret_counter[63:32];
790 `csr_mvendorid: begin
791 csr_output_value = mvendorid;
794 csr_output_value = marchid;
797 csr_output_value = mimpid;
800 csr_output_value = mhartid;
803 csr_output_value = misa;
806 csr_output_value = make_mstatus(mstatus_tsr,
822 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
824 mstatus_mpie = csr_written_value[7];
825 mstatus_mie = csr_written_value[3];
829 csr_output_value = 0;
830 csr_output_value[11] = mie_meie;
831 csr_output_value[9] = mie_seie;
832 csr_output_value[8] = mie_ueie;
833 csr_output_value[7] = mie_mtie;
834 csr_output_value[5] = mie_stie;
835 csr_output_value[4] = mie_utie;
836 csr_output_value[3] = mie_msie;
837 csr_output_value[1] = mie_ssie;
838 csr_output_value[0] = mie_usie;
839 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
841 mie_meie = csr_written_value[11];
842 mie_mtie = csr_written_value[7];
843 mie_msie = csr_written_value[3];
847 csr_output_value = mtvec;
850 csr_output_value = mscratch;
851 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
853 mscratch = csr_written_value;
856 csr_output_value = mepc;
857 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
859 mepc = csr_written_value;
862 csr_output_value = mcause;
863 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
865 mcause = csr_written_value;
868 csr_output_value = 0;
869 csr_output_value[11] = mip_meip;
870 csr_output_value[9] = mip_seip;
871 csr_output_value[8] = mip_ueip;
872 csr_output_value[7] = mip_mtip;
873 csr_output_value[5] = mip_stip;
874 csr_output_value[4] = mip_utip;
875 csr_output_value[3] = mip_msip;
876 csr_output_value[1] = mip_ssip;
877 csr_output_value[0] = mip_usip;
881 write_register(decoder_rd, csr_output_value);
883 else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin