cpu_fetch_stage.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 """
  25
  26 from migen import *
  27 from migen.fhdl import verilog
  28
  29 from riscvdefs import *
  30 from cpudefs import *
  31
  32 reset_vector = 32'hXXXXXXXX;
  33 mtvec = 32'hXXXXXXXX;
  34
  35 class CPUFetchStage(Module):
  36     def __init__(self):
  37         self.clk = ClockSignal()
  38         self.reset = ResetSignal()
  39         #output [31:2] memory_interface_fetch_address,
  40         self.memory_interface_fetch_address = Signal(32)[2:]
  41         #input [31:0] memory_interface_fetch_data,
  42         self.memory_interface_fetch_data = Signal(32)
  43         self.memory_interface_fetch_valid = Signal()
  44         input `fetch_action fetch_action,
  45         input [31:0] target_pc,
  46         self.output_pc = Signal(32, reset=reset_vector)
  47         self.output_instruction = Signal(32)
  48         output reg `fetch_output_state output_state
  49
  50         self.comb += [
  51             self.cd_sys.clk.eq(self.clk),
  52             self.cd_sys.rst.eq(self.reset)
  53         ]
  54
  55         fetch_pc = Signal(32, reset=reset_vector)
  56
  57         self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ? output_pc : fetch_pc);
  58
  59         memory_interface_fetch_address = fetch_pc[2:]
  60
  61         initial output_pc <= reset_vector;
  62         initial output_state <= `fetch_output_state_empty;
  63
  64         delayed_instruction = Signal(32, reset=0);
  65         delayed_instruction_valid = Signal(reset=0);
  66
  67         self.sync += delayed_instruction.eq(output_instruction)
  68         self.sync += output_state.eq(fetch_output_state_empty)
  69
  70         self.comb += output_instruction.eq(delayed_instruction_valid ? delayed_instruction : memory_interface_fetch_data)
  71
  72         self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait)
  73
  74         fc = {}
  75         self.comb += Case(fetch_action, fc)
  76         fc[fetch_action_ack_trap] =
  77                 If(memory_interface_fetch_valid,
  78                    [fetch_pc.eq(fetch_pc + 4),
  79                     output_state.eq(fetch_output_state_valid)]
  80                 ).Else(
  81                    [fetch_pc.eq(mtvec),
  82                     output_state.eq(fetch_output_state_trap)]
  83                 )
  84         fc[fetch_action_default] = fc[fetch_action_ack_trap]
  85         fc[fetch_action_fence] =
  86                 [ fetch_pc.eq(output_pc + 4),
  87                   output_state.eq(fetch_output_state_empty)]
  88         fc[fetch_action_jump] =
  89                 [ fetch_pc.eq(target_pc),
  90                   output_state.eq(fetch_output_state_empty)]
  91         fc[fetch_action_error_trap] =
  92                    [fetch_pc.eq(mtvec),
  93                     output_state.eq(fetch_output_state_empty)]
  94         fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
  95         fc[fetch_action_wait] =
  96                    [fetch_pc.eq(fetch_pc),
  97                     output_state.eq(fetch_output_state_valid)]
  98