more cpu logic

[rv32.git] / README.txt

diff --git a/README.txt b/README.txt
index 611dc57f48b2c343c3211a2ee416b555e5edb44a..c35762314e128a5aa1ecd7353a5a86acc6d33199 100644 (file)
--- a/README.txt
+++ b/README.txt
@@ -1,6 +1,8 @@
 # Limitations
 
 * there is no << or >> operator, only <<< and >>> (arithmetic shift)
+  _Operator("<<", [lhs, rhs]) will generate verilog however simulation
+  will fail, and value_bits_sign will not correctly recognise it
 * it is not possible to declare parameters
 * an input of [31:2] is not possible, only a parameter of [N:0]