move get_fetch_action to separate verilog file

[rv32.git] / README.txt

diff --git a/README.txt b/README.txt
index 611dc57f48b2c343c3211a2ee416b555e5edb44a..ca3ba1ae43b5decb9c11c228300ca4d564d2b33c 100644 (file)
--- a/README.txt
+++ b/README.txt
@@ -1,6 +1,9 @@
 # Limitations
 
 * there is no << or >> operator, only <<< and >>> (arithmetic shift)
+  _Operator("<<", [lhs, rhs]) will generate verilog however simulation
+  will fail, and value_bits_sign will not correctly recognise it
 * it is not possible to declare parameters
 * an input of [31:2] is not possible, only a parameter of [N:0]
-
+* tasks are not supported.
+* Clock Domains: https://gist.github.com/cr1901/5de5b276fca539b66fe7f4493a5bfe7d