add Makefile for verilog compilation

[rv32.git] / README.txt

diff --git a/README.txt b/README.txt
index ec10b2c47f137bb03b540aa6448d212d5f69e2ae..ca3ba1ae43b5decb9c11c228300ca4d564d2b33c 100644 (file)
--- a/README.txt
+++ b/README.txt
@@ -6,3 +6,4 @@
 * it is not possible to declare parameters
 * an input of [31:2] is not possible, only a parameter of [N:0]
 * tasks are not supported.
+* Clock Domains: https://gist.github.com/cr1901/5de5b276fca539b66fe7f4493a5bfe7d