self.meie = Signal(name="mie_meie")
self.mtie = Signal(name="mie_mtie")
self.msie = Signal(name="mie_msie")
+ self.seie = Signal(name="mie_seie")
self.ueie = Signal(name="mie_ueie")
self.stie = Signal(name="mie_stie")
self.utie = Signal(name="mie_utie")
self.sync += self.mtie.eq(0)
self.sync += self.msie.eq(0)
+ def make(self):
+ return Cat( self.usie, self.ssie, 0, self.msie,
+ self.utie, self.stie, 0, self.mtie,
+ self.ueie, self.seie, 0, self.meie, )
+
+
class MIP:
def __init__(self, comb, sync):
self.comb = comb
self.usip = Signal(name="mip_usip")
for n in dir(self):
- if n in ['comb', 'sync'] or n.startswith("_"):
+ if n in ['make', 'comb', 'sync'] or n.startswith("_"):
continue
self.comb += getattr(self, n).eq(0x0)
+ def make(self):
+ return Cat( self.usip, self.ssip, 0, self.msip,
+ self.utip, self.stip, 0, self.mtip,
+ self.ueip, self.seip, 0, self.meip, )
+
class M:
def __init__(self, comb, sync):
self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
self.output_state = Signal(fetch_output_state,name="fetch_output_state")
- def get_fetch_action(self, dc, load_store_misaligned, mi,
- branch_taken, misaligned_jump_target,
- csr_op_is_valid):
+class CSR:
+ def __init__(self, comb, sync, dc, register_rs1):
+ self.comb = comb
+ self.sync = sync
+ self.number = Signal(12, name="csr_number")
+ self.input_value = Signal(32, name="csr_input_value")
+ self.reads = Signal(name="csr_reads")
+ self.writes = Signal(name="csr_writes")
+ self.op_is_valid = Signal(name="csr_op_is_valid")
+
+ self.comb += self.number.eq(dc.immediate)
+ self.comb += self.input_value.eq(Mux(dc.funct3[2],
+ dc.rs1,
+ register_rs1))
+ self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
+ self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
+
+ self.comb += self.get_csr_op_is_valid()
+
+ def get_csr_op_is_valid(self):
+ """ determines if a CSR is valid
+ """
c = {}
- c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
- c[FOS.empty] = self.action.eq(FA.default)
- c[FOS.trap] = self.action.eq(FA.ack_trap)
-
- # illegal instruction -> error trap
- i= If((dc.act & DA.trap_illegal_instruction) != 0,
- self.action.eq(FA.error_trap)
- )
-
- # ecall / ebreak -> noerror trap
- i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
- self.action.eq(FA.noerror_trap))
-
- # load/store: check alignment, check wait
- i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
- If((load_store_misaligned | ~mi.rw_address_valid),
- self.action.eq(FA.error_trap) # misaligned or invalid addr
- ).Elif(mi.rw_wait,
- self.action.eq(FA.wait) # wait
- ).Else(
- self.action.eq(FA.default) # ok
- )
- )
-
- # fence
- i = i.Elif((dc.act & DA.fence) != 0,
- self.action.eq(FA.fence))
-
- # branch -> misaligned=error, otherwise jump
- i = i.Elif((dc.act & DA.branch) != 0,
- If(misaligned_jump_target,
- self.action.eq(FA.error_trap)
- ).Else(
- self.action.eq(FA.jump)
- )
- )
+ # invalid csrs
+ for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
+ csr_uie, csr_utvec, csr_uscratch, csr_uepc,
+ csr_ucause, csr_utval, csr_uip, csr_sstatus,
+ csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
+ csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
+ csr_stval, csr_sip, csr_satp, csr_medeleg,
+ csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
+ c[f] = self.op_is_valid.eq(0)
+
+ # not-writeable -> ok
+ for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
+ csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
+ csr_mimpid, csr_mhartid]:
+ c[f] = self.op_is_valid.eq(~self.writes)
+
+ # valid csrs
+ for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
+ csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
+ c[f] = self.op_is_valid.eq(1)
+
+ # not implemented / default
+ for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
+ csr_mcycleh, csr_minstreth, "default"]:
+ c[f] = self.op_is_valid.eq(0)
+
+ return Case(self.number, c)
+
+ def evaluate_csr_funct3_op(self, funct3, previous, written):
+ c = { "default": written.eq(Constant(0, 32))}
+ for f in [F3.csrrw, F3.csrrwi]:
+ c[f] = written.eq(self.input_value)
+ for f in [F3.csrrs, F3.csrrsi]:
+ c[f] = written.eq(self.input_value | previous)
+ for f in [F3.csrrc, F3.csrrci]:
+ c[f] = written.eq(~self.input_value & previous)
+ return Case(funct3, c)
- # jal/jalr -> misaligned=error, otherwise jump
- i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
- If(misaligned_jump_target,
- self.action.eq(FA.error_trap)
- ).Else(
- self.action.eq(FA.jump)
- )
- )
- # csr -> opvalid=ok, else error trap
- i = i.Elif((dc.act & DA.csr) != 0,
- If(csr_op_is_valid,
- self.action.eq(FA.default)
- ).Else(
- self.action.eq(FA.error_trap)
- )
- )
+class MInfo:
+ def __init__(self, comb):
+ self.comb = comb
+ # TODO
+ self.cycle_counter = Signal(64); # TODO: implement cycle_counter
+ self.time_counter = Signal(64); # TODO: implement time_counter
+ self.instret_counter = Signal(64); # TODO: implement instret_counter
+
+ self.mvendorid = Signal(32)
+ self.marchid = Signal(32)
+ self.mimpid = Signal(32)
+ self.mhartid = Signal(32)
+ self.comb += self.mvendorid.eq(Constant(0, 32))
+ self.comb += self.marchid.eq(Constant(0, 32))
+ self.comb += self.mimpid.eq(Constant(0, 32))
+ self.comb += self.mhartid.eq(Constant(0, 32))
+
+class Regs:
+ def __init__(self, comb, sync):
+ self.comb = comb
+ self.sync = sync
- c[FOS.valid] = i
+ self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en
+ self.rs1 = Signal(32, name="regfile_rs1")
+ self.rs_a = Signal(5, name="regfile_rs_a")
- return Case(self.output_state, c)
+ self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
+ self.rs2 = Signal(32, name="regfile_rs2")
+ self.rs_b = Signal(5, name="regfile_rs_b")
+ self.w_en = Signal(name="regfile_w_en")
+ self.wval = Signal(32, name="regfile_wval")
+ self.rd = Signal(32, name="regfile_rd")
class CPU(Module):
"""
"""
- def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
- """ returns whether a load/store is misaligned
- """
- return Case(funct3[:2],
- { F3.sb: ls.eq(Constant(0)),
- F3.sh: ls.eq(load_store_address_low_2[0] != 0),
- F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
- "default": ls.eq(Constant(1))
- })
-
def get_lsbm(self, dc):
return Cat(Constant(1),
Mux((dc.funct3[1] | dc.funct3[0]),
# return [m.mcause.eq(0),
# ]
- def write_register(self, register_number, value):
- return If(register_number != 0,
- self.registers[register_number].eq(value)
- )
-
- def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
- c = { "default": Constant(0, 32)}
- for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
- for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
- for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
- return Case(funct3, c)
-
def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
s = [ms.mpie.eq(ms.mie),
ms.mie.eq(0),
s.append(i)
return s
- """
- task handle_trap;
- begin
- mstatus_mpie = mstatus_mie;
- mstatus_mie = 0;
- mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
- if(fetch_action == `fetch_action_ack_trap) begin
- mcause = `cause_instruction_access_fault;
- end
- else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
- mcause = `cause_illegal_instruction;
- end
- else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
- mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
- end
- else if((decode_action & `decode_action_load) != 0) begin
- if(load_store_misaligned)
- mcause = `cause_load_address_misaligned;
- else
- mcause = `cause_load_access_fault;
- end
- else if((decode_action & `decode_action_store) != 0) begin
- if(load_store_misaligned)
- mcause = `cause_store_amo_address_misaligned;
- else
- mcause = `cause_store_amo_access_fault;
- end
- else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
- mcause = `cause_instruction_address_misaligned;
- end
- else begin
- mcause = `cause_illegal_instruction;
- end
- end
- endtask
- """
+ def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
+ ft, dc,
+ load_store_misaligned,
+ loaded_value, alu_result,
+ lui_auipc_result):
+ c = {}
+ c[FOS.empty] = []
+ c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
+ load_store_misaligned)
+ c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
+ mstatus, mie, ft, dc,
+ load_store_misaligned,
+ loaded_value,
+ alu_result,
+ lui_auipc_result)
+ return Case(ft.output_state, c)
+
+ def write_register(self, rd, val):
+ return [self.regs.rd.eq(rd),
+ self.regs.wval.eq(val),
+ self.regs.w_en.eq(1)
+ ]
+
+ def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
+ ft, dc,
+ load_store_misaligned,
+ loaded_value, alu_result,
+ lui_auipc_result):
+ # fetch action ack trap
+ i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
+ [self.handle_trap(m, mstatus, ft, dc,
+ load_store_misaligned),
+ self.regs.w_en.eq(0) # no writing to registers
+ ]
+ )
+
+ # load
+ i = i.Elif((dc.act & DA.load) != 0,
+ If(~mi.rw_wait,
+ self.write_register(dc.rd, loaded_value)
+ )
+ )
+
+ # op or op_immediate
+ i = i.Elif((dc.act & DA.op_op_imm) != 0,
+ self.write_register(dc.rd, alu_result)
+ )
+
+ # lui or auipc
+ i = i.Elif((dc.act & DA.lui_auipc) != 0,
+ self.write_register(dc.rd, lui_auipc_result)
+ )
+
+ # jal/jalr
+ i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
+ self.write_register(dc.rd, ft.output_pc + 4)
+ )
+
+ i = i.Elif((dc.act & DA.csr) != 0,
+ self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
+ dc, csr)
+ )
+
+ # fence, store, branch
+ i = i.Elif((dc.act & (DA.fence | DA.fence_i |
+ DA.store | DA.branch)) != 0,
+ # do nothing
+ self.regs.w_en.eq(0) # no writing to registers
+ )
+
+ return i
+
+ def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
+ csr_output_value = Signal(32)
+ csr_written_value = Signal(32)
+ c = {}
+
+ # cycle
+ c[csr_cycle] = csr_output_value.eq(minfo.cycle_counter[0:32])
+ c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
+ # time
+ c[csr_time] = csr_output_value.eq(minfo.time_counter[0:32])
+ c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
+ # instret
+ c[csr_instret] = csr_output_value.eq(minfo.instret_counter[0:32])
+ c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
+ # mvendorid/march/mimpl/mhart
+ c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
+ c[csr_marchid ] = csr_output_value.eq(minfo.marchid )
+ c[csr_mimpid ] = csr_output_value.eq(minfo.mimpid )
+ c[csr_mhartid ] = csr_output_value.eq(minfo.mhartid )
+ # misa
+ c[csr_misa ] = csr_output_value.eq(misa.misa)
+ # mstatus
+ c[csr_mstatus ] = [
+ csr_output_value.eq(mstatus.make()),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ mstatus.mpie.eq(csr_written_value[7]),
+ mstatus.mie.eq(csr_written_value[3])
+ ]
+ # mie
+ c[csr_mie ] = [
+ csr_output_value.eq(mie.make()),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ mie.meie.eq(csr_written_value[11]),
+ mie.mtie.eq(csr_written_value[7]),
+ mie.msie.eq(csr_written_value[3]),
+ ]
+ # mtvec
+ c[csr_mtvec ] = csr_output_value.eq(mtvec)
+ # mscratch
+ c[csr_mscratch ] = [
+ csr_output_value.eq(m.mscratch),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ If(csr.writes,
+ m.mscratch.eq(csr_written_value),
+ )
+ ]
+ # mepc
+ c[csr_mepc ] = [
+ csr_output_value.eq(m.mepc),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ If(csr.writes,
+ m.mepc.eq(csr_written_value),
+ )
+ ]
+
+ # mcause
+ c[csr_mcause ] = [
+ csr_output_value.eq(m.mcause),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ If(csr.writes,
+ m.mcause.eq(csr_written_value),
+ )
+ ]
+
+ # mip
+ c[csr_mip ] = [
+ csr_output_value.eq(mip.make()),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ ]
+
+ return [Case(csr.number, c),
+ If(csr.reads,
+ self.write_register(dc.rd, csr_output_value)
+ )]
def __init__(self):
+ Module.__init__(self)
self.clk = ClockSignal()
self.reset = ResetSignal()
self.tty_write = Signal()
reset_vector.eq(ram_start)
mtvec.eq(ram_start + 0x40)
- l = []
- for i in range(31):
- r = Signal(32, name="register%d" % i)
- l.append(r)
- self.sync += r.eq(Constant(0, 32))
- self.registers = Array(l)
+ self.regs = Regs(self.comb, self.sync)
+
+ rf = Instance("RegFile", name="regfile",
+ i_ra_en = self.regs.ra_en,
+ i_rb_en = self.regs.rb_en,
+ i_w_en = self.regs.w_en,
+ o_read_a = self.regs.rs1,
+ o_read_b = self.regs.rs2,
+ i_writeval = self.regs.wval,
+ i_rs_a = self.regs.rs_a,
+ i_rs_b = self.regs.rs_b,
+ i_rd = self.regs.rd)
+
+ self.specials += rf
mi = MemoryInterface()
)
self.specials += cd
- register_rs1 = Signal(32)
- register_rs2 = Signal(32)
- self.comb += If(dc.rs1 == 0,
- register_rs1.eq(0)
- ).Else(
- register_rs1.eq(self.registers[dc.rs1-1]))
- self.comb += If(dc.rs2 == 0,
- register_rs2.eq(0)
- ).Else(
- register_rs2.eq(self.registers[dc.rs2-1]))
+ self.comb += self.regs.rs_a.eq(dc.rs1)
+ self.comb += self.regs.rs_b.eq(dc.rs2)
load_store_address = Signal(32)
load_store_address_low_2 = Signal(2)
-
- self.comb += load_store_address.eq(dc.immediate + register_rs1)
- self.comb += load_store_address_low_2.eq(
- dc.immediate[:2] + register_rs1[:2])
-
load_store_misaligned = Signal()
+ unmasked_loaded_value = Signal(32)
+ loaded_value = Signal(32)
- lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
- load_store_address_low_2)
- self.comb += lsa
+ lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc",
+ i_dc_immediate = dc.immediate,
+ i_dc_funct3 = dc.funct3,
+ i_rs1 = self.regs.rs1,
+ i_rs2 = self.regs.rs2,
+ i_rw_data_in = mi.rw_data_in,
+ i_rw_data_out = mi.rw_data_out,
+ o_load_store_address = load_store_address,
+ o_load_store_address_low_2 = load_store_address_low_2,
+ o_load_store_misaligned = load_store_misaligned,
+ o_loaded_value = loaded_value)
+
+ self.specials += lsc
# XXX rwaddr not 31:2 any more
self.comb += mi.rw_address.eq(load_store_address[2:])
_Operator("<<", [unshifted_load_store_byte_mask,
load_store_address_low_2]))
- # XXX not obvious
- b3 = Mux(load_store_address_low_2[1],
- Mux(load_store_address_low_2[0], register_rs2[0:8],
- register_rs2[8:16]),
- Mux(load_store_address_low_2[0], register_rs2[16:24],
- register_rs2[24:32]))
- b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
- register_rs2[16:24])
- b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
- register_rs2[8:16])
- b0 = register_rs2[0:8]
-
- self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
-
- # XXX not obvious
- unmasked_loaded_value = Signal(32)
-
- b0 = Mux(load_store_address_low_2[1],
- Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
- mi.rw_data_out[16:24]),
- Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
- mi.rw_data_out[0:8]))
- b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
- mi.rw_data_out[8:16])
- b23 = mi.rw_data_out[16:32]
-
- self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
-
- # XXX not obvious
- loaded_value = Signal(32)
-
- b0 = unmasked_loaded_value[0:8]
- b1 = Mux(dc.funct3[0:2] == 0,
- Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
- unmasked_loaded_value[8:16])
- b2 = Mux(dc.funct3[1] == 0,
- Replicate(~dc.funct3[2] &
- Mux(dc.funct3[0], unmasked_loaded_value[15],
- unmasked_loaded_value[7]),
- 16),
- unmasked_loaded_value[16:32])
-
- self.comb += loaded_value.eq(Cat(b0, b1, b2))
-
self.comb += mi.rw_active.eq(~self.reset
& (ft.output_state == FOS.valid)
& ~load_store_misaligned
alu_b = Signal(32)
alu_result = Signal(32)
- self.comb += alu_a.eq(register_rs1)
+ self.comb += alu_a.eq(self.regs.rs1)
self.comb += alu_b.eq(Mux(dc.opcode[5],
- register_rs2,
+ self.regs.rs2,
dc.immediate))
ali = Instance("cpu_alu", name="alu",
self.comb += ft.target_pc.eq(Cat(0,
Mux(dc.opcode != OP.jalr,
ft.output_pc[1:32],
- register_rs1[1:32] + dc.immediate[1:32])))
+ self.regs.rs1[1:32] + dc.immediate[1:32])))
misaligned_jump_target = Signal()
self.comb += misaligned_jump_target.eq(ft.target_pc[1])
-
+
branch_arg_a = Signal(32)
branch_arg_b = Signal(32)
- self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
- register_rs1[31] ^ ~dc.funct3[1]))
- self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
- register_rs2[31] ^ ~dc.funct3[1]))
+ self.comb += branch_arg_a.eq(Cat( self.regs.rs1[0:31],
+ self.regs.rs1[31] ^ ~dc.funct3[1]))
+ self.comb += branch_arg_b.eq(Cat( self.regs.rs2[0:31],
+ self.regs.rs2[31] ^ ~dc.funct3[1]))
branch_taken = Signal()
self.comb += branch_taken.eq(dc.funct3[0] ^
m = M(self.comb, self.sync)
mstatus = MStatus(self.comb, self.sync)
mie = MIE(self.comb, self.sync)
-
misa = Misa(self.comb, self.sync)
-
- mvendorid = Signal(32)
- marchid = Signal(32)
- mimpid = Signal(32)
- mhartid = Signal(32)
- self.comb += mvendorid.eq(Constant(0, 32))
- self.comb += marchid.eq(Constant(0, 32))
- self.comb += mimpid.eq(Constant(0, 32))
- self.comb += mhartid.eq(Constant(0, 32))
-
mip = MIP(self.comb, self.sync)
- csr_op_is_valid = Signal()
-
- self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
- branch_taken, misaligned_jump_target,
- csr_op_is_valid)
-
- #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
+ # CSR decoding
+ csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
+
+ fi = Instance("CPUFetchAction", name="cpu_fetch_action",
+ o_fetch_action = ft.action,
+ i_output_state = ft.output_state,
+ i_dc_act = dc.act,
+ i_load_store_misaligned = load_store_misaligned,
+ i_mi_rw_wait = mi.rw_wait,
+ i_mi_rw_address_valid = mi.rw_address_valid,
+ i_branch_taken = branch_taken,
+ i_misaligned_jump_target = misaligned_jump_target,
+ i_csr_op_is_valid = csr.op_is_valid)
+
+ self.specials += fi
+
+ minfo = MInfo(self.comb)
+
+ self.sync += If(~self.reset,
+ self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
+ mstatus, mie, ft, dc,
+ load_store_misaligned,
+ loaded_value,
+ alu_result,
+ lui_auipc_result)
+ )
if __name__ == "__main__":
example = CPU()
example.led_1,
example.led_3,
}))
-
-"""
-
- wire [11:0] csr_number = decoder_immediate;
- wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
- wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
- wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
-
- function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
- begin
- case(csr_number)
- `csr_ustatus,
- `csr_fflags,
- `csr_frm,
- `csr_fcsr,
- `csr_uie,
- `csr_utvec,
- `csr_uscratch,
- `csr_uepc,
- `csr_ucause,
- `csr_utval,
- `csr_uip,
- `csr_sstatus,
- `csr_sedeleg,
- `csr_sideleg,
- `csr_sie,
- `csr_stvec,
- `csr_scounteren,
- `csr_sscratch,
- `csr_sepc,
- `csr_scause,
- `csr_stval,
- `csr_sip,
- `csr_satp,
- `csr_medeleg,
- `csr_mideleg,
- `csr_dcsr,
- `csr_dpc,
- `csr_dscratch:
- get_csr_op_is_valid = 0;
- `csr_cycle,
- `csr_time,
- `csr_instret,
- `csr_cycleh,
- `csr_timeh,
- `csr_instreth,
- `csr_mvendorid,
- `csr_marchid,
- `csr_mimpid,
- `csr_mhartid:
- get_csr_op_is_valid = ~csr_writes;
- `csr_misa,
- `csr_mstatus,
- `csr_mie,
- `csr_mtvec,
- `csr_mscratch,
- `csr_mepc,
- `csr_mcause,
- `csr_mip:
- get_csr_op_is_valid = 1;
- `csr_mcounteren,
- `csr_mtval,
- `csr_mcycle,
- `csr_minstret,
- `csr_mcycleh,
- `csr_minstreth:
- // TODO: CSRs not implemented yet
- get_csr_op_is_valid = 0;
- endcase
- end
- endfunction
-
- assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
-
- wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
- wire [63:0] time_counter = 0; // TODO: implement time_counter
- wire [63:0] instret_counter = 0; // TODO: implement instret_counter
-
- always @(posedge clk) begin:main_block
- if(reset) begin
- reset_to_initial();
- disable main_block;
- end
- case(fetch_output_state)
- `fetch_output_state_empty: begin
- end
- `fetch_output_state_trap: begin
- handle_trap();
- end
- `fetch_output_state_valid: begin:valid
- if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
- handle_trap();
- end
- else if((decode_action & `decode_action_load) != 0) begin
- if(~memory_interface_rw_wait)
- write_register(decoder_rd, loaded_value);
- end
- else if((decode_action & `decode_action_op_op_imm) != 0) begin
- write_register(decoder_rd, alu_result);
- end
- else if((decode_action & `decode_action_lui_auipc) != 0) begin
- write_register(decoder_rd, lui_auipc_result);
- end
- else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
- write_register(decoder_rd, fetch_output_pc + 4);
- end
- else if((decode_action & `decode_action_csr) != 0) begin:csr
- reg [31:0] csr_output_value;
- reg [31:0] csr_written_value;
- csr_output_value = 32'hXXXXXXXX;
- csr_written_value = 32'hXXXXXXXX;
- case(csr_number)
- `csr_cycle: begin
- csr_output_value = cycle_counter[31:0];
- end
- `csr_time: begin
- csr_output_value = time_counter[31:0];
- end
- `csr_instret: begin
- csr_output_value = instret_counter[31:0];
- end
- `csr_cycleh: begin
- csr_output_value = cycle_counter[63:32];
- end
- `csr_timeh: begin
- csr_output_value = time_counter[63:32];
- end
- `csr_instreth: begin
- csr_output_value = instret_counter[63:32];
- end
- `csr_mvendorid: begin
- csr_output_value = mvendorid;
- end
- `csr_marchid: begin
- csr_output_value = marchid;
- end
- `csr_mimpid: begin
- csr_output_value = mimpid;
- end
- `csr_mhartid: begin
- csr_output_value = mhartid;
- end
- `csr_misa: begin
- csr_output_value = misa;
- end
- `csr_mstatus: begin
- csr_output_value = make_mstatus(mstatus_tsr,
- mstatus_tw,
- mstatus_tvm,
- mstatus_mxr,
- mstatus_sum,
- mstatus_mprv,
- mstatus_xs,
- mstatus_fs,
- mstatus_mpp,
- mstatus_spp,
- mstatus_mpie,
- mstatus_spie,
- mstatus_upie,
- mstatus_mie,
- mstatus_sie,
- mstatus_uie);
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes) begin
- mstatus_mpie = csr_written_value[7];
- mstatus_mie = csr_written_value[3];
- end
- end
- `csr_mie: begin
- csr_output_value = 0;
- csr_output_value[11] = mie_meie;
- csr_output_value[9] = mie_seie;
- csr_output_value[8] = mie_ueie;
- csr_output_value[7] = mie_mtie;
- csr_output_value[5] = mie_stie;
- csr_output_value[4] = mie_utie;
- csr_output_value[3] = mie_msie;
- csr_output_value[1] = mie_ssie;
- csr_output_value[0] = mie_usie;
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes) begin
- mie_meie = csr_written_value[11];
- mie_mtie = csr_written_value[7];
- mie_msie = csr_written_value[3];
- end
- end
- `csr_mtvec: begin
- csr_output_value = mtvec;
- end
- `csr_mscratch: begin
- csr_output_value = mscratch;
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes)
- mscratch = csr_written_value;
- end
- `csr_mepc: begin
- csr_output_value = mepc;
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes)
- mepc = csr_written_value;
- end
- `csr_mcause: begin
- csr_output_value = mcause;
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes)
- mcause = csr_written_value;
- end
- `csr_mip: begin
- csr_output_value = 0;
- csr_output_value[11] = mip_meip;
- csr_output_value[9] = mip_seip;
- csr_output_value[8] = mip_ueip;
- csr_output_value[7] = mip_mtip;
- csr_output_value[5] = mip_stip;
- csr_output_value[4] = mip_utip;
- csr_output_value[3] = mip_msip;
- csr_output_value[1] = mip_ssip;
- csr_output_value[0] = mip_usip;
- end
- endcase
- if(csr_reads)
- write_register(decoder_rd, csr_output_value);
- end
- else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
- // do nothing
- end
- end
- endcase
- end
-
-endmodule
-"""
-
projects / rv32.git / blobdiff