split out cpu_mie into separate module

[rv32.git] / cpu.py

diff --git a/cpu.py b/cpu.py
index 4b877f499cc9eea1bbdafc3b1303cccc84f3546d..17172c9186b5e8e3e70f7c9bc35fdfe33a4a1bca 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -79,26 +79,7 @@ class MIE:
         self.meie = Signal(name="mie_meie")
         self.mtie = Signal(name="mie_mtie")
         self.msie = Signal(name="mie_msie")
-        self.seie = Signal(name="mie_seie")
-        self.ueie = Signal(name="mie_ueie")
-        self.stie = Signal(name="mie_stie")
-        self.utie = Signal(name="mie_utie")
-        self.ssie = Signal(name="mie_ssie")
-        self.usie = Signal(name="mie_usie")
-
-        for n in dir(self):
-            if n in ['make', 'comb', 'sync'] or n.startswith("_"):
-                continue
-            self.comb += getattr(self, n).eq(0x0)
-
-        self.sync += self.meie.eq(0)
-        self.sync += self.mtie.eq(0)
-        self.sync += self.msie.eq(0)
-
-    def make(self):
-        return Cat( self.usie, self.ssie, 0, self.msie,
-                    self.utie, self.stie, 0, self.mtie,
-                    self.ueie, self.seie, 0, self.meie, )
+        self.mie = Signal(32)
 
 
 class MIP:
@@ -425,7 +406,7 @@ class CPU(Module):
         ]
         # mie
         c[csr_mie      ] = [
-            csr_output_value.eq(mie.make()),
+            csr_output_value.eq(mie.mie),
             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
                                                   csr_written_value),
             mie.meie.eq(csr_written_value[11]),
@@ -666,6 +647,14 @@ class CPU(Module):
         misa = Misa(self.comb, self.sync)
         mip = MIP(self.comb, self.sync)
 
+        mii = Instance("CPUMIE", name="cpu_mie",
+            o_mie = mie.mie,
+            i_meie = mie.meie,
+            i_mtie = mie.mtie,
+            i_msie = mie.msie)
+
+        self.specials += mii
+
         ms = Instance("CPUMStatus", name="cpu_mstatus",
             o_mstatus = mstatus.mstatus,
             i_mpie = mstatus.mpie,