add Makefile for verilog compilation

[rv32.git] / cpu.py

diff --git a/cpu.py b/cpu.py
index 17172c9186b5e8e3e70f7c9bc35fdfe33a4a1bca..29cbe574a8e266a5e5b4c30a666a123696d3e3a4 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -83,28 +83,8 @@ class MIE:
 
 
 class MIP:
-    def __init__(self, comb, sync):
-        self.comb = comb
-        self.sync = sync
-        self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
-        self.seip = Signal(name="mip_seip")
-        self.ueip = Signal(name="mip_uiep")
-        self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
-        self.stip = Signal(name="mip_stip")
-        self.msip = Signal(name="mip_stip")
-        self.utip = Signal(name="mip_utip")
-        self.ssip = Signal(name="mip_ssip")
-        self.usip = Signal(name="mip_usip")
-
-        for n in dir(self):
-            if n in ['make', 'comb', 'sync'] or n.startswith("_"):
-                continue
-            self.comb += getattr(self, n).eq(0x0)
-
-    def make(self):
-        return Cat( self.usip, self.ssip, 0, self.msip,
-                    self.utip, self.stip, 0, self.mtip,
-                    self.ueip, self.seip, 0, self.meip, )
+    def __init__(self):
+        self.mip = Signal(32)
 
 
 class M:
@@ -255,52 +235,11 @@ class CPU(Module):
     #    return [m.mcause.eq(0),
     #            ]
 
-    def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
-        s = [ms.mpie.eq(ms.mie),
-             ms.mie.eq(0),
-             m.mepc.eq(Mux(ft.action == FA.noerror_trap,
-                           ft.output_pc + 4,
-                           ft.output_pc))]
-
-        # fetch action ack trap
-        i = If(ft.action == FA.ack_trap,
-                m.mcause.eq(cause_instruction_access_fault)
-              )
-
-        # ecall/ebreak
-        i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
-                m.mcause.eq(Mux(dc.immediate[0],
-                                cause_machine_environment_call,
-                                cause_breakpoint))
-              )
-
-        # load
-        i = i.Elif((dc.act & DA.load) != 0,
-                If(load_store_misaligned,
-                    m.mcause.eq(cause_load_address_misaligned)
-                ).Else(
-                    m.mcause.eq(cause_load_access_fault)
-                )
-              )
-
-        # store
-        i = i.Elif((dc.act & DA.store) != 0,
-                If(load_store_misaligned,
-                    m.mcause.eq(cause_store_amo_address_misaligned)
-                ).Else(
-                    m.mcause.eq(cause_store_amo_access_fault)
-                )
-              )
-
-        # jal/jalr -> misaligned=error, otherwise jump
-        i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
-                m.mcause.eq(cause_instruction_address_misaligned)
-              )
-
-        # defaults to illegal instruction
-        i = i.Else(m.mcause.eq(cause_illegal_instruction))
-
-        s.append(i)
+    def handle_trap(self, mcause, mepc, mie, mpie):
+        s = [mcause.eq(self.new_mcause),
+             mepc.eq(self.new_mepc),
+             mpie.eq(self.new_mpie),
+             mie.eq(self.new_mie)]
         return s
 
     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
@@ -310,15 +249,17 @@ class CPU(Module):
                          lui_auipc_result):
         c = {}
         c[FOS.empty] = []
-        c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
-                                       load_store_misaligned)
+        c[FOS.trap] = self.handle_trap(m.mcause, m.mepc,
+                                       mstatus.mie, mstatus.mpie)
         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
                                        mstatus, mie, ft, dc,
                                        load_store_misaligned,
                                        loaded_value,
                                        alu_result,
                                        lui_auipc_result)
-        return Case(ft.output_state, c)
+        return [self.regs.w_en.eq(0),
+                Case(ft.output_state, c),
+                self.regs.w_en.eq(0)]
 
     def write_register(self, rd, val):
         return [self.regs.rd.eq(rd),
@@ -333,10 +274,7 @@ class CPU(Module):
                            lui_auipc_result):
         # fetch action ack trap
         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
-                [self.handle_trap(m, mstatus, ft, dc,
-                                       load_store_misaligned),
-                 self.regs.w_en.eq(0) # no writing to registers
-                ]
+                self.handle_trap(m.mcause, m.mepc, mstatus.mie, mstatus.mpie)
               )
 
         # load
@@ -370,7 +308,6 @@ class CPU(Module):
         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
                               DA.store | DA.branch)) != 0,
                 # do nothing
-               self.regs.w_en.eq(0) # no writing to registers
               )
 
         return i
@@ -446,7 +383,7 @@ class CPU(Module):
 
         # mip
         c[csr_mip  ] = [
-            csr_output_value.eq(mip.make()),
+            csr_output_value.eq(mip.mip),
             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
                                                   csr_written_value),
         ]
@@ -645,7 +582,12 @@ class CPU(Module):
         mstatus = MStatus(self.comb, self.sync)
         mie = MIE(self.comb, self.sync)
         misa = Misa(self.comb, self.sync)
-        mip = MIP(self.comb, self.sync)
+        mip = MIP()
+
+        mp = Instance("CPUMIP", name="cpu_mip",
+            o_mip = mip.mip)
+
+        self.specials += mp
 
         mii = Instance("CPUMIE", name="cpu_mie",
             o_mie = mie.mie,
@@ -680,6 +622,25 @@ class CPU(Module):
 
         minfo = MInfo(self.comb)
 
+        self.new_mcause = Signal(32)
+        self.new_mepc = Signal(32)
+        self.new_mpie = Signal()
+        self.new_mie = Signal()
+
+        ht = Instance("CPUHandleTrap", "cpu_handle_trap",
+                      i_ft_action = ft.action,
+                      i_ft_output_pc = ft.output_pc,
+                      i_dc_action = dc.act,
+                      i_dc_immediate = dc.immediate,
+                      i_load_store_misaligned = load_store_misaligned,
+                      i_mie = mstatus.mie,
+                      o_mcause = self.new_mcause,
+                      o_mepc = self.new_mepc,
+                      o_mpie = self.new_mpie,
+                      o_mie = self.new_mie)
+
+        self.specials += ht
+
         self.sync += If(~self.reset,
                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
                                         mstatus, mie, ft, dc,