opcode = Signal(7, name="decoder_opcode")
act = Signal(decode_action, name="decoder_action")
+
class MStatus:
def __init__(self, comb, sync):
self.comb = comb
self.sync = sync
self.mpie = Signal(name="mstatus_mpie")
self.mie = Signal(name="mstatus_mie")
- self.mprv = Signal(name="mstatus_mprv")
- self.tsr = Signal(name="mstatus_tsr")
- self.tw = Signal(name="mstatus_tw")
- self.tvm = Signal(name="mstatus_tvm")
- self.mxr = Signal(name="mstatus_mxr")
- self._sum = Signal(name="mstatus_sum")
- self.xs = Signal(name="mstatus_xs")
- self.fs = Signal(name="mstatus_fs")
- self.mpp = Signal(2, name="mstatus_mpp")
- self.spp = Signal(name="mstatus_spp")
- self.spie = Signal(name="mstatus_spie")
- self.upie = Signal(name="mstatus_upie")
- self.sie = Signal(name="mstatus_sie")
- self.uie = Signal(name="mstatus_uie")
-
- for n in dir(self):
- if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
- continue
- self.comb += getattr(self, n).eq(0x0)
- self.comb += self.mpp.eq(0b11)
+ self.mstatus = Signal(32, name="mstatus")
self.sync += self.mie.eq(0)
self.sync += self.mpie.eq(0)
-
- def make(self):
- return Cat(
- self.uie, self.sie, Constant(0), self.mie,
- self.upie, self.spie, Constant(0), self.mpie,
- self.spp, Constant(0, 2), self.mpp,
- self.fs, self.xs, self.mprv, self._sum,
- self.mxr, self.tvm, self.tw, self.tsr,
- Constant(0, 8),
- (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
- )
+ self.sync += self.mstatus.eq(0)
class MIE:
self.meie = Signal(name="mie_meie")
self.mtie = Signal(name="mie_mtie")
self.msie = Signal(name="mie_msie")
- self.seie = Signal(name="mie_seie")
- self.ueie = Signal(name="mie_ueie")
- self.stie = Signal(name="mie_stie")
- self.utie = Signal(name="mie_utie")
- self.ssie = Signal(name="mie_ssie")
- self.usie = Signal(name="mie_usie")
-
- for n in dir(self):
- if n in ['make', 'comb', 'sync'] or n.startswith("_"):
- continue
- self.comb += getattr(self, n).eq(0x0)
-
- self.sync += self.meie.eq(0)
- self.sync += self.mtie.eq(0)
- self.sync += self.msie.eq(0)
-
- def make(self):
- return Cat( self.usie, self.ssie, 0, self.msie,
- self.utie, self.stie, 0, self.mtie,
- self.ueie, self.seie, 0, self.meie, )
+ self.mie = Signal(32)
class MIP:
- def __init__(self, comb, sync):
- self.comb = comb
- self.sync = sync
- self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
- self.seip = Signal(name="mip_seip")
- self.ueip = Signal(name="mip_uiep")
- self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
- self.stip = Signal(name="mip_stip")
- self.msip = Signal(name="mip_stip")
- self.utip = Signal(name="mip_utip")
- self.ssip = Signal(name="mip_ssip")
- self.usip = Signal(name="mip_usip")
-
- for n in dir(self):
- if n in ['make', 'comb', 'sync'] or n.startswith("_"):
- continue
- self.comb += getattr(self, n).eq(0x0)
-
- def make(self):
- return Cat( self.usip, self.ssip, 0, self.msip,
- self.utip, self.stip, 0, self.mtip,
- self.ueip, self.seip, 0, self.meip, )
+ def __init__(self):
+ self.mip = Signal(32)
class M:
"""
"""
- def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
- """ returns whether a load/store is misaligned
- """
- return Case(funct3[:2],
- { F3.sb: ls.eq(Constant(0)),
- F3.sh: ls.eq(load_store_address_low_2[0] != 0),
- F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
- "default": ls.eq(Constant(1))
- })
-
def get_lsbm(self, dc):
return Cat(Constant(1),
Mux((dc.funct3[1] | dc.funct3[0]),
# return [m.mcause.eq(0),
# ]
- def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
- s = [ms.mpie.eq(ms.mie),
- ms.mie.eq(0),
- m.mepc.eq(Mux(ft.action == FA.noerror_trap,
- ft.output_pc + 4,
- ft.output_pc))]
-
- # fetch action ack trap
- i = If(ft.action == FA.ack_trap,
- m.mcause.eq(cause_instruction_access_fault)
- )
-
- # ecall/ebreak
- i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
- m.mcause.eq(Mux(dc.immediate[0],
- cause_machine_environment_call,
- cause_breakpoint))
- )
-
- # load
- i = i.Elif((dc.act & DA.load) != 0,
- If(load_store_misaligned,
- m.mcause.eq(cause_load_address_misaligned)
- ).Else(
- m.mcause.eq(cause_load_access_fault)
- )
- )
-
- # store
- i = i.Elif((dc.act & DA.store) != 0,
- If(load_store_misaligned,
- m.mcause.eq(cause_store_amo_address_misaligned)
- ).Else(
- m.mcause.eq(cause_store_amo_access_fault)
- )
- )
-
- # jal/jalr -> misaligned=error, otherwise jump
- i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
- m.mcause.eq(cause_instruction_address_misaligned)
- )
-
- # defaults to illegal instruction
- i = i.Else(m.mcause.eq(cause_illegal_instruction))
-
- s.append(i)
+ def handle_trap(self, mcause, mepc, mie, mpie):
+ s = [mcause.eq(self.new_mcause),
+ mepc.eq(self.new_mepc),
+ mpie.eq(self.new_mpie),
+ mie.eq(self.new_mie)]
return s
def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
lui_auipc_result):
c = {}
c[FOS.empty] = []
- c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
- load_store_misaligned)
+ c[FOS.trap] = self.handle_trap(m.mcause, m.mepc,
+ mstatus.mie, mstatus.mpie)
c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
mstatus, mie, ft, dc,
load_store_misaligned,
loaded_value,
alu_result,
lui_auipc_result)
- return Case(ft.output_state, c)
+ return [self.regs.w_en.eq(0),
+ Case(ft.output_state, c),
+ self.regs.w_en.eq(0)]
def write_register(self, rd, val):
return [self.regs.rd.eq(rd),
lui_auipc_result):
# fetch action ack trap
i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
- [self.handle_trap(m, mstatus, ft, dc,
- load_store_misaligned),
- self.regs.w_en.eq(0) # no writing to registers
- ]
+ self.handle_trap(m.mcause, m.mepc, mstatus.mie, mstatus.mpie)
)
# load
i = i.Elif((dc.act & (DA.fence | DA.fence_i |
DA.store | DA.branch)) != 0,
# do nothing
- self.regs.w_en.eq(0) # no writing to registers
)
return i
c[csr_misa ] = csr_output_value.eq(misa.misa)
# mstatus
c[csr_mstatus ] = [
- csr_output_value.eq(mstatus.make()),
+ csr_output_value.eq(mstatus.mstatus),
csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
csr_written_value),
mstatus.mpie.eq(csr_written_value[7]),
]
# mie
c[csr_mie ] = [
- csr_output_value.eq(mie.make()),
+ csr_output_value.eq(mie.mie),
csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
csr_written_value),
mie.meie.eq(csr_written_value[11]),
# mip
c[csr_mip ] = [
- csr_output_value.eq(mip.make()),
+ csr_output_value.eq(mip.mip),
csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
csr_written_value),
]
self.write_register(dc.rd, csr_output_value)
)]
- """
- `csr_mip: begin
- csr_output_value = 0;
- csr_output_value[11] = mip_meip;
- csr_output_value[9] = mip_seip;
- csr_output_value[8] = mip_ueip;
- csr_output_value[7] = mip_mtip;
- csr_output_value[5] = mip_stip;
- csr_output_value[4] = mip_utip;
- csr_output_value[3] = mip_msip;
- csr_output_value[1] = mip_ssip;
- csr_output_value[0] = mip_usip;
- end
- endcase
- end
- endcase
- end
- """
def __init__(self):
Module.__init__(self)
self.clk = ClockSignal()
load_store_address = Signal(32)
load_store_address_low_2 = Signal(2)
-
- self.comb += load_store_address.eq(dc.immediate + self.regs.rs1)
- self.comb += load_store_address_low_2.eq(
- dc.immediate[:2] + self.regs.rs1[:2])
-
load_store_misaligned = Signal()
+ unmasked_loaded_value = Signal(32)
+ loaded_value = Signal(32)
+
+ lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc",
+ i_dc_immediate = dc.immediate,
+ i_dc_funct3 = dc.funct3,
+ i_rs1 = self.regs.rs1,
+ i_rs2 = self.regs.rs2,
+ i_rw_data_in = mi.rw_data_in,
+ i_rw_data_out = mi.rw_data_out,
+ o_load_store_address = load_store_address,
+ o_load_store_address_low_2 = load_store_address_low_2,
+ o_load_store_misaligned = load_store_misaligned,
+ o_loaded_value = loaded_value)
- lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
- load_store_address_low_2)
- self.comb += lsa
+ self.specials += lsc
# XXX rwaddr not 31:2 any more
self.comb += mi.rw_address.eq(load_store_address[2:])
_Operator("<<", [unshifted_load_store_byte_mask,
load_store_address_low_2]))
- # XXX not obvious
- b3 = Mux(load_store_address_low_2[1],
- Mux(load_store_address_low_2[0], self.regs.rs2[0:8],
- self.regs.rs2[8:16]),
- Mux(load_store_address_low_2[0], self.regs.rs2[16:24],
- self.regs.rs2[24:32]))
- b2 = Mux(load_store_address_low_2[1], self.regs.rs2[0:8],
- self.regs.rs2[16:24])
- b1 = Mux(load_store_address_low_2[0], self.regs.rs2[0:8],
- self.regs.rs2[8:16])
- b0 = self.regs.rs2[0:8]
-
- self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
-
- # XXX not obvious
- unmasked_loaded_value = Signal(32)
-
- b0 = Mux(load_store_address_low_2[1],
- Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
- mi.rw_data_out[16:24]),
- Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
- mi.rw_data_out[0:8]))
- b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
- mi.rw_data_out[8:16])
- b23 = mi.rw_data_out[16:32]
-
- self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
-
- # XXX not obvious
- loaded_value = Signal(32)
-
- b0 = unmasked_loaded_value[0:8]
- b1 = Mux(dc.funct3[0:2] == 0,
- Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
- unmasked_loaded_value[8:16])
- b2 = Mux(dc.funct3[1] == 0,
- Replicate(~dc.funct3[2] &
- Mux(dc.funct3[0], unmasked_loaded_value[15],
- unmasked_loaded_value[7]),
- 16),
- unmasked_loaded_value[16:32])
-
- self.comb += loaded_value.eq(Cat(b0, b1, b2))
-
self.comb += mi.rw_active.eq(~self.reset
& (ft.output_state == FOS.valid)
& ~load_store_misaligned
mstatus = MStatus(self.comb, self.sync)
mie = MIE(self.comb, self.sync)
misa = Misa(self.comb, self.sync)
- mip = MIP(self.comb, self.sync)
+ mip = MIP()
+
+ mp = Instance("CPUMIP", name="cpu_mip",
+ o_mip = mip.mip)
+
+ self.specials += mp
+
+ mii = Instance("CPUMIE", name="cpu_mie",
+ o_mie = mie.mie,
+ i_meie = mie.meie,
+ i_mtie = mie.mtie,
+ i_msie = mie.msie)
+
+ self.specials += mii
+
+ ms = Instance("CPUMStatus", name="cpu_mstatus",
+ o_mstatus = mstatus.mstatus,
+ i_mpie = mstatus.mpie,
+ i_mie = mstatus.mie)
+
+ self.specials += ms
# CSR decoding
csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
minfo = MInfo(self.comb)
+ self.new_mcause = Signal(32)
+ self.new_mepc = Signal(32)
+ self.new_mpie = Signal()
+ self.new_mie = Signal()
+
+ ht = Instance("CPUHandleTrap", "cpu_handle_trap",
+ i_ft_action = ft.action,
+ i_ft_output_pc = ft.output_pc,
+ i_dc_action = dc.act,
+ i_dc_immediate = dc.immediate,
+ i_load_store_misaligned = load_store_misaligned,
+ i_mie = mstatus.mie,
+ o_mcause = self.new_mcause,
+ o_mepc = self.new_mepc,
+ o_mpie = self.new_mpie,
+ o_mie = self.new_mie)
+
+ self.specials += ht
+
self.sync += If(~self.reset,
self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
mstatus, mie, ft, dc,
projects / rv32.git / blobdiff