add Makefile for verilog compilation

[rv32.git] / cpu.py

diff --git a/cpu.py b/cpu.py
index fac67d4435b93c473e6bf349aafe228ad238b2dc..29cbe574a8e266a5e5b4c30a666a123696d3e3a4 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -235,6 +235,13 @@ class CPU(Module):
     #    return [m.mcause.eq(0),
     #            ]
 
+    def handle_trap(self, mcause, mepc, mie, mpie):
+        s = [mcause.eq(self.new_mcause),
+             mepc.eq(self.new_mepc),
+             mpie.eq(self.new_mpie),
+             mie.eq(self.new_mie)]
+        return s
+
     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
                          ft, dc,
                          load_store_misaligned,
@@ -242,17 +249,16 @@ class CPU(Module):
                          lui_auipc_result):
         c = {}
         c[FOS.empty] = []
-        c[FOS.trap] = self.handle_trap.eq(1)
+        c[FOS.trap] = self.handle_trap(m.mcause, m.mepc,
+                                       mstatus.mie, mstatus.mpie)
         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
                                        mstatus, mie, ft, dc,
                                        load_store_misaligned,
                                        loaded_value,
                                        alu_result,
                                        lui_auipc_result)
-        return [self.handle_trap.eq(0),
-                self.regs.w_en.eq(0),
+        return [self.regs.w_en.eq(0),
                 Case(ft.output_state, c),
-                self.handle_trap.eq(0),
                 self.regs.w_en.eq(0)]
 
     def write_register(self, rd, val):
@@ -268,9 +274,7 @@ class CPU(Module):
                            lui_auipc_result):
         # fetch action ack trap
         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
-                [self.handle_trap.eq(1),
-                 self.regs.w_en.eq(0) # no writing to registers
-                ]
+                self.handle_trap(m.mcause, m.mepc, mstatus.mie, mstatus.mpie)
               )
 
         # load
@@ -304,7 +308,6 @@ class CPU(Module):
         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
                               DA.store | DA.branch)) != 0,
                 # do nothing
-               self.regs.w_en.eq(0) # no writing to registers
               )
 
         return i
@@ -619,7 +622,10 @@ class CPU(Module):
 
         minfo = MInfo(self.comb)
 
-        self.handle_trap = Signal(reset=0)
+        self.new_mcause = Signal(32)
+        self.new_mepc = Signal(32)
+        self.new_mpie = Signal()
+        self.new_mie = Signal()
 
         ht = Instance("CPUHandleTrap", "cpu_handle_trap",
                       i_ft_action = ft.action,
@@ -627,9 +633,11 @@ class CPU(Module):
                       i_dc_action = dc.act,
                       i_dc_immediate = dc.immediate,
                       i_load_store_misaligned = load_store_misaligned,
-                      o_mcause = m.mcause,
-                      o_mepc = m.mepc,
-                      o_mie = mstatus.mie)
+                      i_mie = mstatus.mie,
+                      o_mcause = self.new_mcause,
+                      o_mepc = self.new_mepc,
+                      o_mpie = self.new_mpie,
+                      o_mie = self.new_mie)
 
         self.specials += ht