split out MStatus to separate module

[rv32.git] / cpu.py

diff --git a/cpu.py b/cpu.py
index 01b4e23fa85b84a3a3cfc73d15802ec4f71fddff..4b877f499cc9eea1bbdafc3b1303cccc84f3546d 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -58,46 +58,18 @@ class Decoder:
     opcode = Signal(7, name="decoder_opcode")
     act = Signal(decode_action, name="decoder_action")
 
+
 class MStatus:
     def __init__(self, comb, sync):
         self.comb = comb
         self.sync = sync
         self.mpie = Signal(name="mstatus_mpie")
         self.mie = Signal(name="mstatus_mie")
-        self.mprv = Signal(name="mstatus_mprv")
-        self.tsr = Signal(name="mstatus_tsr")
-        self.tw = Signal(name="mstatus_tw")
-        self.tvm = Signal(name="mstatus_tvm")
-        self.mxr = Signal(name="mstatus_mxr")
-        self._sum = Signal(name="mstatus_sum")
-        self.xs = Signal(name="mstatus_xs")
-        self.fs = Signal(name="mstatus_fs")
-        self.mpp = Signal(2, name="mstatus_mpp")
-        self.spp = Signal(name="mstatus_spp")
-        self.spie = Signal(name="mstatus_spie")
-        self.upie = Signal(name="mstatus_upie")
-        self.sie = Signal(name="mstatus_sie")
-        self.uie = Signal(name="mstatus_uie")
-
-        for n in dir(self):
-            if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
-                continue
-            self.comb += getattr(self, n).eq(0x0)
-        self.comb += self.mpp.eq(0b11)
+        self.mstatus = Signal(32, name="mstatus")
 
         self.sync += self.mie.eq(0)
         self.sync += self.mpie.eq(0)
-
-    def make(self):
-        return Cat(
-                self.uie, self.sie, Constant(0), self.mie,
-                self.upie, self.spie, Constant(0), self.mpie,
-                self.spp, Constant(0, 2), self.mpp,
-                self.fs, self.xs, self.mprv, self._sum,
-                self.mxr, self.tvm, self.tw, self.tsr,
-                Constant(0, 8),
-                (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
-                )
+        self.sync += self.mstatus.eq(0)
 
 
 class MIE:
@@ -445,7 +417,7 @@ class CPU(Module):
         c[csr_misa     ] = csr_output_value.eq(misa.misa)
         # mstatus
         c[csr_mstatus  ] = [
-            csr_output_value.eq(mstatus.make()),
+            csr_output_value.eq(mstatus.mstatus),
             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
                                                   csr_written_value),
             mstatus.mpie.eq(csr_written_value[7]),
@@ -694,6 +666,13 @@ class CPU(Module):
         misa = Misa(self.comb, self.sync)
         mip = MIP(self.comb, self.sync)
 
+        ms = Instance("CPUMStatus", name="cpu_mstatus",
+            o_mstatus = mstatus.mstatus,
+            i_mpie = mstatus.mpie,
+            i_mie = mstatus.mie)
+
+        self.specials += ms
+
         # CSR decoding
         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)