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rename register varnames to regfile
[rv32.git]
/
cpu.py
diff --git
a/cpu.py
b/cpu.py
index 2f9d22b1af2b8bb4a83a5cdd0c849bbd45d47668..7150968bda422e1cac82a9f29341b360e8731ef0 100644
(file)
--- a/
cpu.py
+++ b/
cpu.py
@@
-337,17
+337,17
@@
class Regs:
self.comb = comb
self.sync = sync
self.comb = comb
self.sync = sync
- self.ra_en = Signal(reset=1
)
- self.r
b_en = Signal(reset=1
)
- self.
wen = Signal(name="register_wen
")
+ self.ra_en = Signal(reset=1
, name="regfile_ra_en") # TODO: ondemand en
+ self.r
s1 = Signal(32, name="regfile_rs1"
)
+ self.
rs_a = Signal(5, name="regfile_rs_a
")
- self.r
s1 = Signal(32, name="register_rs1")
- self.rs2 = Signal(32, name="reg
ister
_rs2")
- self.
wval = Signal(32, name="register_wval
")
+ self.r
b_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
+ self.rs2 = Signal(32, name="reg
file
_rs2")
+ self.
rs_b = Signal(5, name="regfile_rs_b
")
- self.
rs_a = Signal(5, name="register_rs_a
")
- self.
rs_b = Signal(5, name="register_rs_b
")
- self.rd = Signal(32, name="reg
ister
_rd")
+ self.
w_en = Signal(name="regfile_w_en
")
+ self.
wval = Signal(32, name="regfile_wval
")
+ self.rd = Signal(32, name="reg
file
_rd")
class CPU(Module):
"""
class CPU(Module):
"""
@@
-443,7
+443,7
@@
class CPU(Module):
def write_register(self, rd, val):
return [self.regs.rd.eq(rd),
self.regs.wval.eq(val),
def write_register(self, rd, val):
return [self.regs.rd.eq(rd),
self.regs.wval.eq(val),
- self.regs.wen.eq(1)
+ self.regs.w
_
en.eq(1)
]
def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
]
def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
@@
-455,7
+455,7
@@
class CPU(Module):
i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
[self.handle_trap(m, mstatus, ft, dc,
load_store_misaligned),
i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
[self.handle_trap(m, mstatus, ft, dc,
load_store_misaligned),
- self.regs.wen.eq(0) # no writing to registers
+ self.regs.w
_
en.eq(0) # no writing to registers
]
)
]
)
@@
-490,7
+490,7
@@
class CPU(Module):
i = i.Elif((dc.act & (DA.fence | DA.fence_i |
DA.store | DA.branch)) != 0,
# do nothing
i = i.Elif((dc.act & (DA.fence | DA.fence_i |
DA.store | DA.branch)) != 0,
# do nothing
- self.regs.wen.eq(0) # no writing to registers
+ self.regs.w
_
en.eq(0) # no writing to registers
)
return i
)
return i
@@
-619,7
+619,7
@@
class CPU(Module):
rf = Instance("RegFile", name="regfile",
i_ra_en = self.regs.ra_en,
i_rb_en = self.regs.rb_en,
rf = Instance("RegFile", name="regfile",
i_ra_en = self.regs.ra_en,
i_rb_en = self.regs.rb_en,
- i_w_en = self.regs.wen,
+ i_w_en = self.regs.w
_
en,
o_read_a = self.regs.rs1,
o_read_b = self.regs.rs2,
i_writeval = self.regs.wval,
o_read_a = self.regs.rs1,
o_read_b = self.regs.rs2,
i_writeval = self.regs.wval,