return Case(self.output_state, c)
+class CSR:
+ def __init__(self, comb, sync, dc, register_rs1):
+ self.comb = comb
+ self.sync = sync
+ self.number = Signal(12, name="csr_number")
+ self.input_value = Signal(32, name="csr_input_value")
+ self.reads = Signal(name="csr_reads")
+ self.writes = Signal(name="csr_writes")
+ self.op_is_valid = Signal(name="csr_op_is_valid")
+
+ self.comb += self.number.eq(dc.immediate)
+ self.comb += self.input_value.eq(Mux(dc.funct3[2],
+ dc.rs1,
+ register_rs1))
+ self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
+ self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
+
+ self.comb += self.get_csr_op_is_valid()
+
+ def get_csr_op_is_valid(self):
+ """ determines if a CSR is valid
+ """
+ c = {}
+ # invalid csrs
+ for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
+ csr_uie, csr_utvec, csr_uscratch, csr_uepc,
+ csr_ucause, csr_utval, csr_uip, csr_sstatus,
+ csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
+ csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
+ csr_stval, csr_sip, csr_satp, csr_medeleg,
+ csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
+ c[f] = self.op_is_valid.eq(0)
+
+ # not-writeable -> ok
+ for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
+ csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
+ csr_mimpid, csr_mhartid]:
+ c[f] = self.op_is_valid.eq(~self.writes)
+
+ # valid csrs
+ for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
+ csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
+ c[f] = self.op_is_valid.eq(1)
+
+ # not implemented / default
+ for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
+ csr_mcycleh, csr_minstreth, "default"]:
+ c[f] = self.op_is_valid.eq(0)
+
+ return Case(self.number, c)
+
+ def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
+ c = { "default": Constant(0, 32)}
+ for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
+ for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
+ for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
+ return Case(funct3, c)
+
+
+class MInfo:
+ def __init__(self, comb):
+ self.comb = comb
+ # TODO
+ self.cycle_counter = Signal(64); # TODO: implement cycle_counter
+ self.time_counter = Signal(64); # TODO: implement time_counter
+ self.instret_counter = Signal(64); # TODO: implement instret_counter
+
+ self.mvendorid = Signal(32)
+ self.marchid = Signal(32)
+ self.mimpid = Signal(32)
+ self.mhartid = Signal(32)
+ self.comb += self.mvendorid.eq(Constant(0, 32))
+ self.comb += self.marchid.eq(Constant(0, 32))
+ self.comb += self.mimpid.eq(Constant(0, 32))
+ self.comb += self.mhartid.eq(Constant(0, 32))
+
class CPU(Module):
"""
self.registers[register_number].eq(value)
)
- def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
- c = { "default": Constant(0, 32)}
- for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
- for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
- for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
- return Case(funct3, c)
-
def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
s = [ms.mpie.eq(ms.mie),
ms.mie.eq(0),
s.append(i)
return s
- """
- task handle_trap;
- begin
- mstatus_mpie = mstatus_mie;
- mstatus_mie = 0;
- mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
- if(fetch_action == `fetch_action_ack_trap) begin
- mcause = `cause_instruction_access_fault;
- end
- else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
- mcause = `cause_illegal_instruction;
- end
- else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
- mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
- end
- else if((decode_action & `decode_action_load) != 0) begin
- if(load_store_misaligned)
- mcause = `cause_load_address_misaligned;
- else
- mcause = `cause_load_access_fault;
- end
- else if((decode_action & `decode_action_store) != 0) begin
- if(load_store_misaligned)
- mcause = `cause_store_amo_address_misaligned;
- else
- mcause = `cause_store_amo_access_fault;
- end
- else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
- mcause = `cause_instruction_address_misaligned;
- end
- else begin
- mcause = `cause_illegal_instruction;
+ def main_block(self, minfo, csr, mi, m, mstatus, ft, dc,
+ load_store_misaligned,
+ loaded_value, alu_result,
+ lui_auipc_result):
+ c = {}
+ c[FOS.empty] = []
+ c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
+ load_store_misaligned)
+ c[FOS.valid] = self.handle_valid(minfo, csr, mi, m, mstatus, ft, dc,
+ load_store_misaligned,
+ loaded_value,
+ alu_result,
+ lui_auipc_result)
+ return Case(ft.output_state, c)
+
+ def handle_valid(self, minfo, csr, mi, m, mstatus, ft, dc,
+ load_store_misaligned,
+ loaded_value, alu_result,
+ lui_auipc_result):
+ # fetch action ack trap
+ i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
+ self.handle_trap(m, mstatus, ft, dc,
+ load_store_misaligned)
+ )
+
+ # load
+ i = i.Elif((dc.act & DA.load) != 0,
+ If(~mi.rw_wait,
+ self.write_register(dc.rd, loaded_value)
+ )
+ )
+
+ # op or op_immediate
+ i = i.Elif((dc.act & DA.op_op_imm) != 0,
+ self.write_register(dc.rd, alu_result)
+ )
+
+ # lui or auipc
+ i = i.Elif((dc.act & DA.lui_auipc) != 0,
+ self.write_register(dc.rd, lui_auipc_result)
+ )
+
+ # jal/jalr
+ i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
+ self.write_register(dc.rd, ft.output_pc + 4)
+ )
+
+ i = i.Elif((dc.act & DA.csr) != 0,
+ self.handle_csr(minfo, mstatus, dc, csr)
+ )
+
+ # fence, store, branch
+ i = i.Elif((dc.act & (DA.fence | DA.fence_i |
+ DA.store | DA.branch)) != 0,
+ # do nothing
+ )
+
+ return i
+
+ def handle_csr(self, minfo, mstatus, dc, csr):
+ csr_output_value = Signal()
+ csr_written_value = Signal()
+ c = {}
+
+ return Case(csr.number, c)
+
+ """
+ reg [31:0] csr_output_value;
+ reg [31:0] csr_written_value;
+ csr_output_value = 32'hXXXXXXXX;
+ csr_written_value = 32'hXXXXXXXX;
+ case(csr_number)
+ `csr_cycle: begin
+ csr_output_value = cycle_counter[31:0];
+ end
+ `csr_time: begin
+ csr_output_value = time_counter[31:0];
+ end
+ `csr_instret: begin
+ csr_output_value = instret_counter[31:0];
+ end
+ `csr_cycleh: begin
+ csr_output_value = cycle_counter[63:32];
+ end
+ `csr_timeh: begin
+ csr_output_value = time_counter[63:32];
+ end
+ `csr_instreth: begin
+ csr_output_value = instret_counter[63:32];
+ end
+ `csr_mvendorid: begin
+ csr_output_value = mvendorid;
+ end
+ `csr_marchid: begin
+ csr_output_value = marchid;
+ end
+ `csr_mimpid: begin
+ csr_output_value = mimpid;
+ end
+ `csr_mhartid: begin
+ csr_output_value = mhartid;
+ end
+ `csr_misa: begin
+ csr_output_value = misa;
+ end
+ `csr_mstatus: begin
+ csr_output_value = make_mstatus(mstatus_tsr,
+ mstatus_tw,
+ mstatus_tvm,
+ mstatus_mxr,
+ mstatus_sum,
+ mstatus_mprv,
+ mstatus_xs,
+ mstatus_fs,
+ mstatus_mpp,
+ mstatus_spp,
+ mstatus_mpie,
+ mstatus_spie,
+ mstatus_upie,
+ mstatus_mie,
+ mstatus_sie,
+ mstatus_uie);
+ csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
+ if(csr_writes) begin
+ mstatus_mpie = csr_written_value[7];
+ mstatus_mie = csr_written_value[3];
+ end
+ end
+ `csr_mie: begin
+ csr_output_value = 0;
+ csr_output_value[11] = mie_meie;
+ csr_output_value[9] = mie_seie;
+ csr_output_value[8] = mie_ueie;
+ csr_output_value[7] = mie_mtie;
+ csr_output_value[5] = mie_stie;
+ csr_output_value[4] = mie_utie;
+ csr_output_value[3] = mie_msie;
+ csr_output_value[1] = mie_ssie;
+ csr_output_value[0] = mie_usie;
+ csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
+ if(csr_writes) begin
+ mie_meie = csr_written_value[11];
+ mie_mtie = csr_written_value[7];
+ mie_msie = csr_written_value[3];
+ end
+ end
+ `csr_mtvec: begin
+ csr_output_value = mtvec;
+ end
+ `csr_mscratch: begin
+ csr_output_value = mscratch;
+ csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
+ if(csr_writes)
+ mscratch = csr_written_value;
+ end
+ `csr_mepc: begin
+ csr_output_value = mepc;
+ csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
+ if(csr_writes)
+ mepc = csr_written_value;
+ end
+ `csr_mcause: begin
+ csr_output_value = mcause;
+ csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
+ if(csr_writes)
+ mcause = csr_written_value;
+ end
+ `csr_mip: begin
+ csr_output_value = 0;
+ csr_output_value[11] = mip_meip;
+ csr_output_value[9] = mip_seip;
+ csr_output_value[8] = mip_ueip;
+ csr_output_value[7] = mip_mtip;
+ csr_output_value[5] = mip_stip;
+ csr_output_value[4] = mip_utip;
+ csr_output_value[3] = mip_msip;
+ csr_output_value[1] = mip_ssip;
+ csr_output_value[0] = mip_usip;
+ end
+ endcase
+ if(csr_reads)
+ write_register(decoder_rd, csr_output_value);
+ end
end
+ endcase
end
- endtask
- """
-
+ """
def __init__(self):
self.clk = ClockSignal()
self.reset = ResetSignal()
m = M(self.comb, self.sync)
mstatus = MStatus(self.comb, self.sync)
mie = MIE(self.comb, self.sync)
-
misa = Misa(self.comb, self.sync)
-
- mvendorid = Signal(32)
- marchid = Signal(32)
- mimpid = Signal(32)
- mhartid = Signal(32)
- self.comb += mvendorid.eq(Constant(0, 32))
- self.comb += marchid.eq(Constant(0, 32))
- self.comb += mimpid.eq(Constant(0, 32))
- self.comb += mhartid.eq(Constant(0, 32))
-
mip = MIP(self.comb, self.sync)
- csr_op_is_valid = Signal()
+ # CSR decoding
+ csr = CSR(self.comb, self.sync, dc, register_rs1)
self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
branch_taken, misaligned_jump_target,
- csr_op_is_valid)
+ csr.op_is_valid)
+
+ minfo = MInfo(self.comb)
- #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
+ self.sync += If(~self.reset,
+ self.main_block(minfo, csr, mi, m, mstatus, ft, dc,
+ load_store_misaligned,
+ loaded_value,
+ alu_result,
+ lui_auipc_result)
+ )
if __name__ == "__main__":
example = CPU()
"""
- wire [11:0] csr_number = decoder_immediate;
- wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
- wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
- wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
-
- function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
- begin
- case(csr_number)
- `csr_ustatus,
- `csr_fflags,
- `csr_frm,
- `csr_fcsr,
- `csr_uie,
- `csr_utvec,
- `csr_uscratch,
- `csr_uepc,
- `csr_ucause,
- `csr_utval,
- `csr_uip,
- `csr_sstatus,
- `csr_sedeleg,
- `csr_sideleg,
- `csr_sie,
- `csr_stvec,
- `csr_scounteren,
- `csr_sscratch,
- `csr_sepc,
- `csr_scause,
- `csr_stval,
- `csr_sip,
- `csr_satp,
- `csr_medeleg,
- `csr_mideleg,
- `csr_dcsr,
- `csr_dpc,
- `csr_dscratch:
- get_csr_op_is_valid = 0;
- `csr_cycle,
- `csr_time,
- `csr_instret,
- `csr_cycleh,
- `csr_timeh,
- `csr_instreth,
- `csr_mvendorid,
- `csr_marchid,
- `csr_mimpid,
- `csr_mhartid:
- get_csr_op_is_valid = ~csr_writes;
- `csr_misa,
- `csr_mstatus,
- `csr_mie,
- `csr_mtvec,
- `csr_mscratch,
- `csr_mepc,
- `csr_mcause,
- `csr_mip:
- get_csr_op_is_valid = 1;
- `csr_mcounteren,
- `csr_mtval,
- `csr_mcycle,
- `csr_minstret,
- `csr_mcycleh,
- `csr_minstreth:
- // TODO: CSRs not implemented yet
- get_csr_op_is_valid = 0;
- endcase
- end
- endfunction
-
- assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
-
- wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
- wire [63:0] time_counter = 0; // TODO: implement time_counter
- wire [63:0] instret_counter = 0; // TODO: implement instret_counter
-
always @(posedge clk) begin:main_block
if(reset) begin
reset_to_initial();
projects / rv32.git / blobdiff