"""
def __init__(self):
- self.instruction = Signal(32)
- self.funct7 = Signal(7)
- self.funct3 = Signal(3)
- self.rd = Signal(5)
- self.rs1 = Signal(5)
- self.rs2 = Signal(5)
- self.immediate = Signal(32)
- self.opcode = Signal(7)
- self.decode_action = Signal(decode_action)
+ #self.clk = ClockSignal()
+ #self.reset = ResetSignal()
+ self.tty_write = Signal()
+ self.tty_write_data = Signal(8)
+ self.tty_write_busy = Signal()
+ self.switch_2 = Signal()
+ self.switch_3 = Signal()
+ self.led_1 = Signal()
+ self.led_3 = Signal()
+
+ ram_size = Constant(0x8000)
+ ram_start = Constant(0x10000, 32)
+ reset_vector = Signal(32)
+ mtvec = Signal(32)
+
+ reset_vector.eq(ram_start)
+ mtvec.eq(ram_start + 0x40)
+
+ l = []
+ for i in range(31):
+ l.append(Signal(32, name="register%d" % i))
+ registers = Array(l)
+
+ #self.sync += self.registers[0].eq(0)
+ #self.sync += self.registers[1].eq(0)
+
+ memory_interface_fetch_address = Signal(32) # XXX [2:]
+ memory_interface_fetch_data = Signal(32)
+ memory_interface_fetch_valid = Signal()
+ memory_interface_rw_address= Signal(32) # XXX [2:]
+ memory_interface_rw_byte_mask = Signal(4)
+ memory_interface_rw_read_not_write = Signal()
+ memory_interface_rw_active = Signal()
+ memory_interface_rw_data_in = Signal(32)
+ memory_interface_rw_data_out = Signal(32)
+ memory_interface_rw_address_valid = Signal()
+ memory_interface_rw_wait = Signal()
+
+ mi = Instance("cpu_memory_interface", name="memory_instance",
+ p_ram_size = ram_size,
+ p_ram_start = ram_start,
+ i_clk=ClockSignal(),
+ i_rst=ResetSignal(),
+ i_fetch_address = memory_interface_fetch_address,
+ o_fetch_data = memory_interface_fetch_data,
+ o_fetch_valid = memory_interface_fetch_valid,
+ i_rw_address = memory_interface_rw_address,
+ i_rw_byte_mask = memory_interface_rw_byte_mask,
+ i_rw_read_not_write = memory_interface_rw_read_not_write,
+ i_rw_active = memory_interface_rw_active,
+ i_rw_data_in = memory_interface_rw_data_in,
+ o_rw_data_out = memory_interface_rw_data_out,
+ o_rw_address_valid = memory_interface_rw_address_valid,
+ o_rw_wait = memory_interface_rw_wait,
+ o_tty_write = self.tty_write,
+ o_tty_write_data = self.tty_write_data,
+ i_tty_write_busy = self.tty_write_busy,
+ i_switch_2 = self.switch_2,
+ i_switch_3 = self.switch_3,
+ o_led_1 = self.led_1,
+ o_led_3 = self.led_3
+ )
+ self.specials += mi
+
+ fetch_act = Signal(fetch_action)
+ fetch_target_pc = Signal(32)
+ fetch_output_pc = Signal(32)
+ fetch_output_instruction = Signal(32)
+ fetch_output_st = Signal(fetch_output_state)
+
+ fs = Instance("CPUFetchStage", name="fetch_stage",
+ i_clk=ClockSignal(),
+ i_rst=ResetSignal(),
+ o_memory_interface_fetch_address = memory_interface_fetch_address,
+ i_memory_interface_fetch_data = memory_interface_fetch_data,
+ i_memory_interface_fetch_valid = memory_interface_fetch_valid,
+ i_fetch_action = fetch_act,
+ i_target_pc = fetch_target_pc,
+ o_output_pc = fetch_output_pc,
+ o_output_instruction = fetch_output_instruction,
+ o_output_state = fetch_output_st,
+ i_reset_vector = reset_vector,
+ i_mtvec = mtvec,
+ )
+ self.specials += fs
+
+ decoder_funct7 = Signal(7)
+ decoder_funct3 = Signal(3)
+ decoder_rd = Signal(5)
+ decoder_rs1 = Signal(5)
+ decoder_rs2 = Signal(5)
+ decoder_immediate = Signal(32)
+ decoder_opcode = Signal(7)
+ decode_act = Signal(decode_action)
+
+ cd = Instance("CPUDecoder", name="decoder",
+ i_instruction = fetch_output_instruction,
+ o_funct7 = decoder_funct7,
+ o_funct3 = decoder_funct3,
+ o_rd = decoder_rd,
+ o_rs1 = decoder_rs1,
+ o_rs2 = decoder_rs2,
+ o_immediate = decoder_immediate,
+ o_opcode = decoder_opcode,
+ o_decode_action = decode_act
+ )
+ self.specials += cd
+
+ register_rs1 = Signal(32)
+ register_rs2 = Signal(32)
+ self.comb += If(decoder_rs1 == 0,
+ register_rs1.eq(0)
+ ).Else(
+ register_rs1.eq(registers[decoder_rs1-1]))
+ self.comb += If(decoder_rs2 == 0,
+ register_rs2.eq(0)
+ ).Else(
+ register_rs2.eq(registers[decoder_rs2-1]))
+
+ load_store_address = Signal(32)
+ load_store_address_low_2 = Signal(2)
+
+ self.comb += load_store_address.eq(decoder_immediate + register_rs1)
+ self.comb += load_store_address_low_2.eq(
+ decoder_immediate[:2] + register_rs1[:2])
if __name__ == "__main__":
- example = CPUDecoder()
+ example = CPU()
print(verilog.convert(example,
{
- example.clk,
- example.reset,
example.tty_write,
example.tty_write_data,
example.tty_write_busy,
}))
"""
-module cpu(
- input clk,
- input reset,
- output tty_write,
- output [7:0] tty_write_data,
- input tty_write_busy,
- input switch_2,
- input switch_3,
- output led_1,
- output led_3
- );
-
- parameter ram_size = 'h8000;
- parameter ram_start = 32'h1_0000;
- parameter reset_vector = ram_start;
- parameter mtvec = ram_start + 'h40;
-
- reg [31:0] registers[31:1];
-
- wire [31:2] memory_interface_fetch_address;
- wire [31:0] memory_interface_fetch_data;
- wire memory_interface_fetch_valid;
- wire [31:2] memory_interface_rw_address;
- wire [3:0] memory_interface_rw_byte_mask;
- wire memory_interface_rw_read_not_write;
- wire memory_interface_rw_active;
- wire [31:0] memory_interface_rw_data_in;
- wire [31:0] memory_interface_rw_data_out;
- wire memory_interface_rw_address_valid;
- wire memory_interface_rw_wait;
-
- cpu_memory_interface #(
- .ram_size(ram_size),
- .ram_start(ram_start)
- ) memory_interface(
- .clk(clk),
- .reset(reset),
- .fetch_address(memory_interface_fetch_address),
- .fetch_data(memory_interface_fetch_data),
- .fetch_valid(memory_interface_fetch_valid),
- .rw_address(memory_interface_rw_address),
- .rw_byte_mask(memory_interface_rw_byte_mask),
- .rw_read_not_write(memory_interface_rw_read_not_write),
- .rw_active(memory_interface_rw_active),
- .rw_data_in(memory_interface_rw_data_in),
- .rw_data_out(memory_interface_rw_data_out),
- .rw_address_valid(memory_interface_rw_address_valid),
- .rw_wait(memory_interface_rw_wait),
- .tty_write(tty_write),
- .tty_write_data(tty_write_data),
- .tty_write_busy(tty_write_busy),
- .switch_2(switch_2),
- .switch_3(switch_3),
- .led_1(led_1),
- .led_3(led_3)
- );
-
- wire `fetch_action fetch_action;
- wire [31:0] fetch_target_pc;
- wire [31:0] fetch_output_pc;
- wire [31:0] fetch_output_instruction;
- wire `fetch_output_state fetch_output_state;
-
- cpu_fetch_stage #(
- .reset_vector(reset_vector),
- .mtvec(mtvec)
- ) fetch_stage(
- .clk(clk),
- .reset(reset),
- .memory_interface_fetch_address(memory_interface_fetch_address),
- .memory_interface_fetch_data(memory_interface_fetch_data),
- .memory_interface_fetch_valid(memory_interface_fetch_valid),
- .fetch_action(fetch_action),
- .target_pc(fetch_target_pc),
- .output_pc(fetch_output_pc),
- .output_instruction(fetch_output_instruction),
- .output_state(fetch_output_state)
- );
-
- wire [6:0] decoder_funct7;
- wire [2:0] decoder_funct3;
- wire [4:0] decoder_rd;
- wire [4:0] decoder_rs1;
- wire [4:0] decoder_rs2;
- wire [31:0] decoder_immediate;
- wire [6:0] decoder_opcode;
- wire `decode_action decode_action;
-
- cpu_decoder decoder(
- .instruction(fetch_output_instruction),
- .funct7(decoder_funct7),
- .funct3(decoder_funct3),
- .rd(decoder_rd),
- .rs1(decoder_rs1),
- .rs2(decoder_rs2),
- .immediate(decoder_immediate),
- .opcode(decoder_opcode),
- .decode_action(decode_action));
-
- wire [31:0] register_rs1 = (decoder_rs1 == 0) ? 0 : registers[decoder_rs1];
- wire [31:0] register_rs2 = (decoder_rs2 == 0) ? 0 : registers[decoder_rs2];
-
- wire [31:0] load_store_address = decoder_immediate + register_rs1;
-
- wire [1:0] load_store_address_low_2 = decoder_immediate[1:0] + register_rs1[1:0];
function get_load_store_misaligned(
input [2:0] funct3,
projects / rv32.git / blobdiff